Kaiyuan Yang is an Associate Professor in the Department of Electrical and Computer Engineering at Rice University, leading the Secure and Intelligent Micro-Systems (SIMS) Lab. His research focuses on low-power integrated circuits and bioelectronic implants for applications like the Internet of Everything and medical devices. He holds a B.S. from Tsinghua University (2012) and M.S./Ph.D. degrees from the University of Michigan (2017). Research Interests: Low-power digital/analog/mixed-signal systems Bioelectronics and implantable devices Hardware security and PUF design Mixed-signal computing and emerging materials Recent work emphasizes magnetoelectric-powered implants, secure backscatter communication, and in-memory computing architectures. His publications span top venues like IEEE ISSCC, IEDM, and ACM MobiCom. Awards: 2022 NSF CAREER Award 2022 IEEE Top Picks in Hardware Security 2016 IEEE SSCS Predoctoral Achievement Award Dr. Yang serves on editorial boards for IEEE TVLSI and program committees for ISSCC/CICC. His lab develops miniature, secure, and energy-efficient systems for healthcare and IoT applications.
Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.
Dr. Akhilesh Jaiswal serves as Assistant Professor of Electrical and Computer Engineering at the University of Wisconsin-Madison, where his research pioneers device-circuit co-design for next-generation computing systems. His work focuses on enabling extreme-edge intelligence through processing-in-pixel technology, in-memory computing architectures, and bio-inspired neuromorphic systems. His academic credentials include: PhD in Nano-electronics from Purdue University (2019) MS from the University of Minnesota (2014) Bachelor of Technology from Shri Guru Gobind Singhji Institute of Engineering and Technology (2011) Dr. Jaiswal's research program centers on revolutionizing edge computing through hardware innovations that integrate sensing and processing. His device-circuit co-design approach leverages alternate state variables to create energy-efficient systems for real-time applications, with particular emphasis on retina-inspired sensors and photonic memory architectures. This work bridges semiconductor physics with AI acceleration needs, targeting applications from autonomous systems to biomedical devices. Analysis of his 2023-2025 publications reveals dominant themes in photonic SRAM-based in-memory computing (40% of output), retina-inspired motion processing (30%), and secure hardware architectures (20%). His team consistently develops novel bitcell designs that enable XOR logic execution within memory arrays while maintaining compatibility with CMOS fabrication processes. Recent work shows increasing focus on biomedical applications of processing-in-pixel technology. His distinguished recognition includes: Three consecutive ISI Exploratory Research Awards (2020-2023) IEEE Brain Community Best Paper Award (2022) 27 issued US patents with multiple pending applications Nomination for USC Moore Inventor Fellowship (2022) Dr. Jaiswal actively mentors graduate researchers through ECE 790/890/990 courses while securing exploratory funding through ISI and Keston Foundation awards. His patent portfolio demonstrates exceptional translational impact, with industry game-changer classifications from USPTO. The 2022 VLSI-SoC nomination and multiple research highlights in major outlets validate his contributions to hardware security and neuromorphic vision sensors. His laboratory develops integrated hardware platforms combining magnetic tunnel junctions, photonic memory, and CMOS image sensors to create unified processing-in-sensor systems. Current projects include retina-inspired motion segmentation for event cameras and electro-optic frequency transducers for quantum computing interfaces, with strong industry collaboration through patent licensing.
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
Kristofer Pister is a Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He co-directs the Berkeley Sensor and Actuator Center (BSAC) and the Ubiquitous Swarm Lab. His career spans groundbreaking innovations in Micro/Nano Electro Mechanical Systems (MEMS), Control Systems, and Low-Power Circuits, with a focus on Smart Dust and synthetic insects. Education: Ph.D. and M.S. in EECS from UC Berkeley (1992, 1989); B.A. in Applied Physics from UC San Diego (1986). His research areas include MEMS , Control Systems , Robotics , and Integrated Circuits , with recent work on self-powered micro-sensors, crystal-free radios, and interplanetary swarm networks. Key awards include the ISA Albert F. Sperry Founder Award (2009) , Alexander Schwarzkopf Prize (2006) , and the NSF CAREER Award (1996) . He has authored numerous influential publications in wireless sensor networks and microrobotics. His lab, Ubiquitous Swarm Lab , explores distributed robotics and swarm intelligence. Pister emphasizes open collaboration in research, ethical conduct in academia, and efficient resource utilization for graduate students.
Professor Bharat Bhuva is a faculty member in the School of Engineering at Vanderbilt University, holding the position of Professor of Electrical Engineering and Computer Engineering . His research focuses on radiation effects on integrated circuits, semiconductor device modeling, and VLSI design, with an emphasis on advancing the resilience of nanoscale electronics against single-event effects and total-ionizing-dose damage. He also investigates emerging technologies like FinFET and FDSOI for improved radiation hardness and performance. Education: Ph.D. in Electrical Engineering, North Carolina State University M.S. in Electrical Engineering, North Carolina State University B.S. in Electrical Engineering, Maharaja Sayajirao University Research Interests: Professor Bhuva’s work spans computer-aided design tools, semiconductor process modeling, and the mitigation of radiation-induced failures in advanced integrated circuits. His studies address challenges posed by scaling to smaller technology nodes (e.g., 3-nm FinFET) and the impact of environmental factors like temperature, bias conditions, and neutron exposure on circuit reliability. Key areas include multicell upsets, single-event upset (SEU) cross-section analysis, and the efficacy of radiation-hardened-by-design (RHBD) techniques. Awards & Recognition: None explicitly listed in the provided text. However, his extensive publications in top-tier journals like IEEE Transactions on Nuclear Science highlight his contributions to the field. Grants & Advising: Advises on projects related to advanced semiconductor technologies and radiation effects. His research has been supported by grants from institutions focusing on space electronics and nanotechnology. No specific grant details or student advisees are listed. Labs & Teams: Likely affiliated with Vanderbilt’s Cyber-physical Systems and Nano Science and Technology research neighborhoods, though specific lab names are not mentioned in the text.
Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.
Daniele Ielmini is a Professor at the Department of Electronics, Information and Bioengineering at Politecnico di Milano, Italy, where he leads research in non-volatile memory technologies and neuromorphic computing. He received his Laurea (with merit) and Ph.D. in Nuclear Engineering from Politecnico di Milano in 1995 and 2000, respectively, and has held visiting positions at Intel Corporation (2006), Stanford University (2006), and the University of Illinois at Urbana-Champaign (2010). His research focuses on the modeling and characterization of non-volatile memories, including nanocrystal memory, charge trap memory, phase change memory (PCM), resistive switching memory (RRAM), and spin-transfer torque magnetic memory (STT-MRAM). He has co-edited the book 'Resistive switching – from fundamental redox-processes to device applications' and published over 300 papers with more than 10,000 citations and an H-index of 69 (Scopus, September 2023). Prof. Ielmini's recent publications demonstrate a strong trend toward in-memory computing and neuromorphic applications, with particular emphasis on closed-loop analog computing architectures, reservoir computing with 2D materials, and hardware security implementations using emerging memory technologies. His work bridges fundamental device physics with practical computing applications, especially for energy-efficient AI acceleration. Intel Outstanding Researcher Award (2013) ERC Consolidator Grant (2014) IEEE-EDS Paul Rappaport Award (2015) Fellow of the IEEE Prof. Ielmini leads multiple ERC-funded projects including SHANNON (Secure Hardware with Advanced Nonvolatile memories), NEURO2D (neuromorphic systems based on reservoir computing in MoS2), and ANIMATE (closed-loop in-memory computing). His research group includes post-doctoral researchers, PhD students, and M.Sc. students working on various aspects of emerging memory technologies and their applications. He serves as Associate Editor for IEEE Trans. Nanotechnology and Semiconductor Science and Technology (IOP), and has served in several Technical Subcommittees of international conferences including IEEE-IEDM, IEEE-IRPS, and IEEE-ISCAS. His laboratory at Politecnico di Milano is equipped with advanced semiconductor device testing equipment including probe-stations, semiconductor parameter analyzers, high-speed waveform generators, and other specialized instruments for nano-electronic research. The lab collaborates with major semiconductor companies including Micron Technology Inc. and STMicroelectronics, as well as participating in national and international research projects.
Said Hamdioui serves as a full Professor in the Department of Computer Engineering within the Faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology. His research focuses on cutting-edge hardware architectures for neuromorphic computing and energy-efficient AI acceleration, with particular emphasis on memristor-based systems, emerging memory technologies, and fault-tolerant designs for edge applications. His research interests span Neuromorphic Computing , Memristor-Based Architectures , and Energy-Efficient AI Hardware , addressing critical challenges in hardware security, computation-in-memory, and reliable edge AI deployment. Recent work demonstrates significant advancements in RRAM/FeFET testing methodologies, spiking neural network implementations, and spin wave computing alternatives to traditional CMOS. His publications reveal strong trends toward real-world deployment of brain-inspired hardware with practical constraints like power efficiency, testability, and security. Award highlights include: DATE'20 Best Paper Award DFT'21 Outstanding Student Paper ETS 2021 Best Paper Award LATS 2018 & 2022 Best Paper Awards Professor Hamdioui actively contributes to the research community through editorial roles at IEEE Transactions on VLSI Systems , IEEE Design & Test , and Journal of Electronic Testing from 2017-2018. His leadership in multi-partner projects like CONVOLVE and NEUROKIT2E demonstrates strong industry-academia collaboration for edge AI solutions. Current work shows increasing focus on practical deployment challenges including in-field fault monitoring, security vulnerabilities in neuromorphic systems, and realistic brain simulation frameworks.
Kaushik Nayak is an Associate Professor in the Department of Electrical Engineering at the Indian Institute of Technology Hyderabad . His research spans semiconductor device physics, mesoscopic electronics, and electro-thermal effects in nanoscale transistors, with recent work on diamond MOSFETs, 2D material contacts, and thermal resistance in nano-sheet FETs. Ph.D., Indian Institute of Technology Bombay M. Tech., Microelectronics, IIT Bombay B.E., Electronics & Telecommunication, Utkal University He teaches advanced courses on semiconductor device modeling, mesoscopic electronics, and electromagnetic wave propagation. His publications focus on nanoelectronics, device variability, and high-temperature operations. Contact: knayak@ee.iith.ac.in .
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Hossein Valavi is a Lecturer and Assistant Director of Undergraduate Studies at Princeton University, contributing to advancements in computer architecture and hardware acceleration. His research focuses on in-memory computing, neural networks, and energy-efficient systems, with notable work in reconfigurable architectures and mixed-signal processing. He has received multiple teaching awards, including recognition for innovative pandemic-era Car Lab courses and collaborative work honored by the Edison Patent Award. His academic contributions span academic positions since 2018, emphasizing both research and pedagogical excellence. Key technical areas include scalable in-memory computing systems, analog neural network accelerators, and low-power matrix factorization algorithms. His work addresses critical challenges in data movement reduction and hardware-software co-design for modern computing systems. Awards: Teaching Excellence Awards (2021, 2023), Edison Patent Award (2023) Grants & Projects: Leading developments in in-memory computing accelerators and embedded microprocessor designs Research teams under his guidance have produced impactful IP in semiconductor layouts, CNN accelerators, and programmable architectures, aiming to bridge theoretical computer science with practical hardware implementations.
Jeyavijayan 'JV' Rajendran is an Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University, part of the College of Engineering. He is an ASCEND Fellow and leads the Secure and Trustworthy Hardware (SETH) Lab. His research focuses on hardware security, computer security, and novel applications of AI in secure hardware design. Education: PhD in Electrical Engineering (NYU 2015), MS in Computer Engineering (NYU Tandon 2010), BE in Electronics and Communication Engineering (Anna University 2008). Research Interests: Hardware Security, Computer Security, Logic Locking, Hardware IP Protection, and Reinforcement Learning for Security. He explores AI-driven approaches to detect vulnerabilities, protect intellectual property, and enhance secure hardware design through fuzzing, obfuscation, and formal verification. Notable Awards: 2022 Office of Naval Research Young Investigator Award, 2021 IEEE CEDA Ernest Kuh Early Career Award, 2017 NSF CAREER Award. Lab and Teams: The SETH Lab focuses on trustworthy hardware design, developing techniques to secure integrated circuits against reverse engineering and IP theft. Current projects include LLM-based hardware code generation, formal approaches for hardware fuzzing, and AI-driven vulnerability detection.
Wenfeng Zhao is an Assistant Professor in the Department of Electrical and Computer Engineering at Binghamton University. He holds a PhD from the National University of Singapore (2014) and BS/MS degrees from Huazhong University of Science and Technology (2007-2009). Prior to this role, he conducted postdoctoral research at the University of Minnesota's Biomedical Engineering Department. His research focuses on neural engineering, compressed sensing, ultra-low-power VLSI systems, and in-memory computing. Key areas include hardware security, biomedical signal processing, and energy-efficient computing architectures. His work spans applications in neural interfaces, cryptographic hardware, and IoT edge devices. Recent publications highlight advancements in block-cipher-in-memory architectures, emotion recognition via EEG analysis, and energy-efficient FPGA accelerators for neural networks. His research also addresses challenges in cryogenic memory systems and MRI-compatible neural recording devices. Zhao's contributions emphasize interdisciplinary approaches at the intersection of hardware design, signal processing, and cybersecurity. His lab develops novel solutions for low-power embedded systems and trustworthy IoT infrastructure.
Sani Nassif is a Research Fellow at the Technical University of Munich (TUM) under the Rudolf Diesel Industry Fellowship, hosted by Professor Ulf Schlichtmann. With 28 years of experience at Bell Labs and IBM Research, he has led teams in integrated circuit modeling, simulation, statistical analysis, and optimization. Research Interests: His work bridges integrated circuit technology with cross-disciplinary applications in medicine. Key areas include variability analysis in semiconductor manufacturing, low-power circuit design, and reliability engineering for nano-scale systems. He focuses on applying machine learning and statistical methods to solve challenges in energy-efficient computing and biomedical systems. Selected Publications: His research spans circuit variability trends, leakage current modeling, and reliability frameworks for nano-era systems. Work includes foundational studies on SRAM failure analysis and CMOS scaling limitations. Scientific Awards: He is recognized as an IEEE Fellow IBM Master Inventor (75 patents) Rudolf Diesel Industry Fellow
