David W Parent

David W Parent serves as Professor in the Electrical Engineering Department at San José State University's College of Engineering. He holds office ENGR 355 with contact (408) 924-3963 and email david.parent@sjsu.edu. As co-Principal Investigator and Project Coordinator for Project Engineering Success—a five-year, $5 million Department of Education grant—he leads initiatives to improve Hispanic and low-income student outcomes in engineering and computer science through partnerships with San Jose City College and Gavilan Community College.

Professor Parent's research spans two critical domains: semiconductor device engineering and innovative engineering education. His technical work focuses on neuromorphic circuits, particularly ReRAM implementations, semiconductor fabrication, MOS devices, solar cells, and MEMS technologies. His education research targets student success mechanisms for underrepresented populations, including directed self-placement exams, transfer student pathways, and faculty development for inclusive teaching practices. The Microscale Process Engineering Laboratory under his direction supports hands-on semiconductor research.

Analysis of his recent publications reveals a strategic shift toward addressing systemic barriers in engineering education while maintaining technical expertise. His work demonstrates growing emphasis on Hispanic student retention, community college transfer pathways, and faculty development programs—complementing his ongoing contributions to neuromorphic hardware design. This dual focus creates meaningful bridges between advanced technical research and practical educational interventions.

As co-PI of Project Engineering Success, Parent manages multiple grant-funded activities including the 3-Day Summer Faculty Workshop (focused on active learning strategies for diverse classrooms), Model Transfer Curriculum Pathways development, and industry outreach programs with partners like SEMI. He provides critical leadership in creating structured support systems that help students rapidly progress through core engineering courses at SJSU and partner institutions.

Professor Parent directs several key project components: Activity 3 (Faculty Development), Activity 4 (Transfer Pathways), and Activity 5 (Industry Outreach). His laboratory work in the Microscale Process Engineering Laboratory continues to advance semiconductor research while his educational innovations reach beyond campus through partnerships with community colleges and industry. He maintains active research profiles on Research Gate, ORCID, and Google Scholar while developing course materials for EE110/EE110L and providing student success guidance for electrical engineering coursework.