معرفی
Dr. Alexandre Joannou is a Senior Research Software Engineer at the Department of Computer Science and Technology, University of Cambridge. His research focuses on secure hardware-software co-design, particularly in the CHERI (Capability Hardware Enhanced RISC Instructions) project. He specializes in computer architecture, memory safety, and RISC-V processors, with a focus on integrating security into low-level system components.
His work spans theoretical contributions to capability-based systems and practical implementations in accelerators, GPUs, and embedded devices. Key areas include secure speculation, memory protection, and formal verification of hardware designs. Joannou's research has advanced temporal safety in heaps, compressed capabilities for efficiency, and architectural contracts to prevent vulnerabilities.
His publications emphasize hardware security innovations, including CHERI-RISC-V integration, GPGPU memory protection, and randomized testing methodologies. Collaborations involve both academic and industry partners in secure computing ecosystems.
