Dr. Alexandre Joannou is a Senior Research Software Engineer at the Department of Computer Science and Technology, University of Cambridge. His research focuses on secure hardware-software co-design, particularly in the CHERI (Capability Hardware Enhanced RISC Instructions) project. He specializes in computer architecture, memory safety, and RISC-V processors, with a focus on integrating security into low-level system components. His work spans theoretical contributions to capability-based systems and practical implementations in accelerators, GPUs, and embedded devices. Key areas include secure speculation, memory protection, and formal verification of hardware designs. Joannou's research has advanced temporal safety in heaps, compressed capabilities for efficiency, and architectural contracts to prevent vulnerabilities. His publications emphasize hardware security innovations, including CHERI-RISC-V integration, GPGPU memory protection, and randomized testing methodologies. Collaborations involve both academic and industry partners in secure computing ecosystems.
Alexander Hepp serves as a Lecturer at the Chair of Security in Information Technology, Technical University of Munich (TUM), where he contributes to both teaching and cutting-edge hardware security research. His current teaching responsibilities include C++ Lab, Embedded Systems and Security, and Strategic Management for Engineers, where he acts as primary lecturer for the latter course. His research centers on hardware trojan design/identification and netlist reverse engineering within the chair's broader security initiatives. His research portfolio demonstrates deep specialization in hardware security vulnerabilities, with emphasis on hardware trojan insertion/detection methodologies and reverse engineering countermeasures. Recent work explores neuro engineering applications and RISC-V-based security implementations, often leveraging open-source hardware frameworks. His publications reveal consistent innovation in hardware obfuscation techniques and netlist analysis tools, addressing critical gaps in pre-silicon security validation. His 12 publications from 2021-2024 show strong focus on hardware security conferences like DATE and DDECS, with recurring themes in trojan detection, reverse engineering challenges, and cryptographic hardware validation. The research trajectory indicates growing emphasis on practical countermeasures against physical attacks and standardized vulnerability assessment frameworks. Scientific Awards: Best Paper Award at DDECS 2022 for 'Hardware Obfuscation of Digital FIR Filters' No verifiable information exists regarding student advising or grant funding in available sources. He operates within Prof. Sigl's research ecosystem which actively pursues projects in fault attacks, IoT security, physical unclonable functions, and post-quantum cryptography implementations, with recent work emphasizing hardware reverse engineering challenges in advanced semiconductor designs.
Professor Gizopoulos Dimitris is a faculty member at the Department of Informatics and Telecommunications, National and Kapodistrian University of Athens. His research focuses on advanced topics in computer architecture, reliability engineering, and hardware security. With a strong emphasis on fault tolerance and computational integrity, his work addresses critical challenges in modern computing systems such as silent data corruptions, GPU reliability, and RISC-V cloud ecosystems. Key research interests include microarchitecture-level analysis, cross-layer system reliability assessment, and energy-efficient computing. His contributions span fault propagation modeling, hardware-software co-design for resilience, and innovative approaches to detecting silent errors in CPUs and GPUs. He actively participates in large-scale projects like NEUROPULS and Vitamin-V, advancing secure neuromorphic architectures and open-source cloud infrastructure. Recent publications highlight trends in silent data corruption quantification, GPU vulnerability analysis, and energy-efficient RISC-V designs. His work bridges theoretical models with practical implementations, emphasizing real-world validation through frameworks like gem5 and fault injection experiments. Despite no listed advisees or grants in current records, his research collaborations and project leadership position him at the forefront of next-generation computing reliability. Labs and teams associated with his work include the Vitamin-V virtual environment development team and the NEUROPULS consortium for secure neuromorphic accelerators. These initiatives reflect his commitment to advancing both theoretical and applied aspects of dependable computing systems.
David Mallasen Quintana is a Scientist and Lecturer at the Swiss Federal Institute of Technology Lausanne (EPFL), affiliated with both the School of Engineering (STI) and the Integrated Systems Laboratory (ESL) within the Institute of Electrical and Microengineering. He also holds teaching responsibilities in the School of Computer and Communication Sciences (IC) at EPFL. Dr. Quintana completed his Ph.D. in Computer Engineering at Universidad Complutense de Madrid in 2024. His research focuses on: Computer architecture and arithmetic systems RISC-V ecosystem development and customization Energy-efficient hardware design and domain-specific accelerators Posit arithmetic implementations and optimizations Embedded systems and low-power computing solutions His recent publications demonstrate consistent focus on RISC-V extensions, posit arithmetic implementations, and hardware/software co-design approaches for efficient computing. The work spans from fundamental arithmetic units to application-specific accelerators, with evolving emphasis on scientific computing applications and energy-constrained environments. Dr. Quintana actively contributes to open-source hardware projects including PERCIVAL, x-HEEP, and various arithmetic unit implementations. His research group develops energy-efficient platforms and tools for hardware deployment within the RISC-V ecosystem.
Francisco Tirado is a Full Professor of Computer Architecture at Complutense University of Madrid since 1986. He has held leadership roles including Vice-Chancellor for Research (2012-2015), Dean of the Faculty of Physics (1994-2002), and Director of the Complutense Supercomputing Center (2002-2007). He is a founding member of the Spanish Society for Computer Science (SCIE) and Spanish Society for Computer Architecture (SARTECO). His research focuses on power-aware computing, heterogeneous systems, bioinformatics, and hardware design automation. He has authored over 242 publications and supervised 15 PhD theses. His professional service includes chairing 138 international conferences and serving on numerous committees for EUROMICRO, IEEE, and national research agencies. Education: No explicit details provided, but has been active at Complutense University since 1978. Affiliations: Member of COSCE Executive Board (2012), IEEE Senior Member (2005), and EUROMICRO Board (1991-2004). Research Interests: - Optimizing energy efficiency in high-performance computing systems - Design of heterogeneous architectures and accelerators - Bioinformatics applications through hardware/software co-design - Parallel programming models for emerging architectures - Automation tools for FPGA and embedded systems development Conference Contributions: Played multiple roles (General Chair, Program Chair) for major events like ParCo, HPCA, and EUROMICRO PDP conferences. Delivered 64 keynote/plenary lectures globally. Scientific Awards: Doctor 'Honoris Causa' from universities in Spain, Paraguay, and Peru 2013 National Computer Science Award IEEE Senior Membership Advising: Supervised 15 PhD students. Active in technology transfer contracts with industry. Labs/Teams: Founder and leader of the ArTeCS research group at Complutense University, specializing in computer architecture and high-performance computing innovations.
Philipp van Kempen is a researcher at the Chair of Design Automation (Prof. Schlichtmann) at the Technical University of Munich. His work focuses on electronic design automation, specifically targeting RISC-V architecture, TinyML optimization, and LLVM compiler infrastructure for custom hardware accelerators. Key Research Areas: RISC-V ISA extensions, autovectorization, neural network accelerators, and compiler toolchain automation. Collaborations: Works with Daniel Mueller-Gritschneder, Ulf Schlichtmann, and Jefferson Parker Jones. His recent publications highlight contributions to benchmarking TinyML CNN kernels on RISC-V vector hardware, developing semi-automated LLVM support for ISA extensions, and optimizing TinyML inference through frameworks like MLonMCU and muRISCV-NN.
Conrad Foik is a researcher at the Chair of Electronic Design Automation at the Technical University of Munich , working under Prof. Dr.-Ing. Ulf Schlichtmann. His research focuses span analog and digital design automation, processor modeling, and performance simulation. University: Technical University of Munich Department: Electronic Design Automation Research Areas: Processor Description Languages, Software Performance Simulation, Hardware-Software Co-Design His recent work addresses flexible generation of performance simulators, mapping instruction set models to hardware, and RISC-V simulation environments. Publications highlight tools like CorePerfDSL for accurate performance modeling.
Jürgen Teich is a Professor at the University of Erlangen-Nuremberg, Department of Computer Science. His research focuses on computer architecture, embedded systems, and hardware-software co-design, with particular emphasis on energy-efficient and sustainable computing. He leads projects involving FPGA-based accelerators, neural networks on microcontrollers, and real-time systems optimization. His work spans topics such as approximation computing, MPSoCs (Multiprocessor Systems-on-Chip), and IoT device architectures. Key contributions include methodologies for optimizing resource allocation in heterogeneous systems and developing energy-harvesting solutions for embedded systems. Teich has authored numerous publications in top-tier conferences and journals, including DATE, FPL, and ACM Transactions. His research often collaborates with industry partners, emphasizing practical applications and open-source hardware.
Dionysios Pneumatikatos is a Professor at the School of Electrical and Computer Engineering of the National Technical University of Athens (NTUA) since September 2019. Previously, he served as a Professor and Chair of the Department of Electronic and Computing Engineering at the Technical University of Crete (2000–2019) and is an Associate Researcher at the Foundation for Research and Technology (FORTH) since 1997. His primary affiliations include the Computing Systems Laboratory (CSLab) at NTUA and the Computer Architecture and VLSI Systems (CARV) Laboratory at FORTH. Education: B.Sc. in Computer Science, University of Crete (1989) M.Sc. and Ph.D. in Computer Science, University of Wisconsin–Madison (1991, 1995) Research Interests: Computer Architecture Reconfigurable Computing Hardware Acceleration (e.g., FPGA, RISC-V) Energy-Efficient Systems Reliable System Design Application-Specific Architectures His work focuses on heterogeneous parallel systems , bioinformatics accelerators , and virtualization frameworks for reconfigurable platforms . Recent Projects & Contributions: Coordinator of the FASTER (FP7) project Principal Investigator in EDRA (H2020), EXTRA , and dReDBox Key roles in AXIOM , DeSyRe , and VPLANET These projects explore FPGA-based HPC systems , RISC-V ecosystems , and disaggregated data center architectures . Teaching & Mentorship: Teaches courses on Computer Architecture , Parallel Processing , and Logic Design at NTUA and TU Crete Supervised multiple national/EU projects, fostering interdisciplinary research in embedded and high-performance systems Labs & Networks: Active member of the HiPEAC European Network Program Committee roles at ISCA , FPL , and DATE Led the 21st International Conference on Field-Programmable Logic and Applications (FPL)
Sophia Shao is an Associate Professor in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. She was promoted to Associate Professor with tenure in July 2024 after serving as an Assistant Professor from August 2019 to June 2024. Previously, she worked as a Senior Research Scientist at NVIDIA from October 2018 to July 2019. Her academic journey began with a Bachelor of Electrical Engineering from Zhejiang University, China (2005-2009), followed by a Master of Science (2009-2014) and Ph.D. (2009-2016) in Computer Science from Harvard University. Shao's research focuses on computer architecture, with special emphasis on domain-specific accelerators, heterogeneous architecture, and agile VLSI design methodology. Her work bridges the gap between hardware and software through systematic approaches to accelerator design and evaluation. She leads research efforts in the Agile Design of Efficient Processing Technologies (ADEPT), Berkeley Emerging Technologies Research (BETR), Berkeley Wireless Research Center (BWRC), and SpeciaLIzed Computing Ecosystems (SLICE) centers. Her recent publications reveal a strong trend toward holistic hardware-software co-design for machine learning acceleration, with particular focus on efficient neural network accelerators, multi-tenant execution environments, and automated design methodologies. Her research spans from low-level circuit design to system-level architecture, demonstrating expertise across the entire computing stack. Notably, her work on Gemmini, Stellar, and Virgo represents significant contributions to the field of domain-specific accelerator design and integration. Sloan Research Fellowship (2024) Anita Borg Early Career Award (2024) NSF CAREER Award (2023) Google Research Scholar Award (2023) IEEE TCCA Young Computer Architect Award (2022) Intel Rising Star Faculty Award (2022) ISCA Distinguished Artifact Award (2023, 2024) Best Paper Award at DAC 2021 Professor Shao actively mentors a large group of graduate and undergraduate students, with several former students now at leading technology companies including NVIDIA, Microsoft, and Apple. Her research has been supported by multiple grants from NSF, Google, Intel, and other organizations. She leads several open-source research projects including Gemmini, Stellar, Chipyard, and RoSÉ, which have gained significant traction in both academic and industrial research communities. Her lab, part of the SLICE ecosystem, focuses on creating next-generation computing platforms through vertically integrated hardware-software approaches.
Francisco Fabio Banchelli Gracia is a researcher affiliated with the Universitat Politècnica de Catalunya (UPC), specifically in the Department of Systems, Automation, and Industrial Informatics at the Barcelona School of Informatics (FIB). He is actively involved in high-performance computing (HPC) research and collaborates with the Barcelona Supercomputing Center (BSC). His research interests include high-performance computing, computer architecture, energy efficiency in computing systems, performance analysis of HPC and computational fluid dynamics (CFD) workloads, Arm-based processors (A64FX, ThunderX2), RISC-V, hardware-software co-design, and HPC education for undergraduates. His work bridges industry practices and academic training, particularly in introducing students to real-world HPC environments. The recent publications highlight a strong focus on evaluating emerging HPC architectures such as NVIDIA Grace and Arm-based systems, developing generic performance and efficiency models, benchmarking production CFD codes, and advancing educational methodologies for HPC. His work spans both technical innovation and pedagogical development in the HPC domain. He has contributed to major HPC conferences such as the International Conference on High Performance Computing (HiPC), Platform for Advanced Scientific Computing (PASC), IEEE Cluster, and IEEE/ACM workshops on HPC education. His collaborations are primarily with researchers at UPC and BSC, especially Filippo Mantovani and Marta Garcia Gasulla. Francisco Fabio Banchelli Gracia is actively engaged in research and publication, with no indication of retirement or former status. He advises on HPC education initiatives and participates in collaborative research projects, though specific grants are not detailed in the provided text. He is part of the CAP (High Performance Computing Group) and works within the UPC-BSC ecosystem, contributing to cutting-edge HPC system evaluation and educational outreach.
Professor Liam McDaid serves as Interim Research Director at Ulster University's School of Computing, Engineering and Intelligent Systems (Magee Campus, Derry~Londonderry). His leadership spans computational neuroscience and neuromorphic engineering projects addressing global challenges through the UN Sustainable Development Goals framework. Research focuses on computational neuroscience and neural engineering , with expertise in spiking neural networks, astrocyte modeling, hardware implementations (FPGAs/Networks-on-Chip), and biomedical applications. His work integrates computer hardware with biological systems for fault-tolerant computing and medical diagnostics. Key publications reveal trends in neuromorphic hardware for real-time fault detection (RISC-V systems), medical AI for cardiac/adrenal diagnostics, and event-driven sensing . Research bridges computer engineering with neuroscience to solve healthcare infrastructure challenges. Prize 'Biotechnology' category in Northern Ireland Science Park 25K Award (2011) IgniteNI's global Accelerator Programme (2021) Life and Health Startup Company of the Year 2019 (InventNI) Prize Asthma (2019) Leads major projects including AI-EPOCMON (cardiac diagnostics), Nervous Systems (neural interfaces), and microwave thermal therapy for hypertension. Supervises PhD researchers in neural engineering while directing industry collaborations with healthcare technology focus. Maintains active partnerships across Europe in neuromorphic computing and medical device development. Directs research teams advancing spiking neural networks for hardware security and medical applications, with recent work on adrenal segmentation pipelines and RISC-V watchdog mechanisms. Future initiatives focus on expanding AI-driven point-of-care diagnostics and neuromorphic infrastructure monitoring systems.
Christos Kotselidis is an Associate Professor at the University of Manchester's School of Computer Science and serves as Chief Engineer at Pierer Innovation (previously mentioned as KTM Innovation). He leads the TornadoVM project, a groundbreaking Java Virtual Machine for heterogeneous hardware acceleration. His work bridges academia and industry, focusing on hardware/software co-design for virtual machines and embedded systems. His research spans chip design, micro-architecture, compilers, virtual machines, and garbage collection. Dr. Kotselidis has pioneered work in heterogeneous computing, particularly in accelerating Java applications on GPUs, FPGAs, and RISC-V architectures. His team's recent development of GPULlama3.java demonstrates the practical application of his research in bringing LLM inference to pure Java with GPU acceleration. His publications show a consistent focus on bridging hardware capabilities with managed runtime systems. The research trajectory reveals increasing sophistication in handling memory hierarchies, parallelism, and cross-architecture execution. His work has significant implications for high-performance computing, AI acceleration, and sustainable computing practices. Dr. Kotselidis actively contributes to the academic community as a program committee member for conferences like ISMM and as an organizer for workshops including VMIL and MoreVMs. He's also involved in EU-funded projects like AERO and DARE, which focus on European processor initiatives and software ecosystems. As project lead for TornadoVM, he mentors a research team at Manchester including Michalis Papadimitriou, Mary Xekalaki, and Thanos Stratikopoulos. His lab (Beehive Lab) develops open-source tools that are widely used in both academic and industrial settings for heterogeneous computing.
George Papadimitriou is an Assistant Professor in the Computer Engineering & Informatics Department at the University of Patras , Greece, hosted within the School of Engineering . His primary affiliation lies with the Computer Hardware and Architecture division, where he leads research and teaching activities focused on dependable, energy-efficient computer architectures. Education: PhD in Computer Science, Department of Informatics & Telecommunications, National and Kapodistrian University of Athens (2019) Post-doctoral researcher, Computer Architecture Lab, National and Kapodistrian University of Athens Research Interests: Dr Papadimitriou’s research lies at the intersection of computer architecture , energy efficiency , and microprocessor reliability . His work specifically targets: Robust and energy-efficient CPU/GPU/accelerator architectures Post-silicon validation techniques for catching elusive hardware bugs Silent data corruption detection and mitigation across the compute stack Characterization of voltage margins and power consumption in modern microprocessors Modeling and simulation of domain-specific accelerators for low-power, dependable operation More recently, his team has been extending these methodologies to RISC-V and neuromorphic photonic accelerators within large European consortia. Scientific Awards & Recognition: Eight HiPEAC Paper Awards for top-tier conference publications (MICRO, HPCA, ISCA) between 2017–2024 IEEE Transactions on Computers 2022 Best Paper Award for the article “Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers” TTTC/ITC Gerald W. Gordon Student Award 2023 Research Funding & Projects: Dr Papadimitriou is principal investigator or key technical contributor in multiple Horizon Europe and industry-backed projects that collectively exceed €50 M in funding. Current leadership roles include: DARE (Digital Autonomy for RISC-V in Europe) NEUROPULS (Neuromorphic Energy-Efficient Secure Accelerators) REBECCA (Reconfigurable Heterogeneous Highly Parallel Processing Platform) Vitamin-V (Virtual Environment & Tool-boxing for Trustworthy RISC-V Cloud Services) Intel, IBM, and Thales bilateral research contracts on energy-efficient and resilient microarchitectures Laboratory & Team: He leads the Energy-Efficient and Dependable Architectures (EEDA) research group at University of Patras, operating laboratory facilities for silicon measurement, FPGA emulation, and full-system simulation (gem5, MARSS, custom tools). The team currently comprises 3 PhD candidates, 2 post-docs, and several MSc thesis students collaborating with European and US partners.
David Mallasén Quintana is a Postdoctoral Researcher in Computer Engineering at the Embedded Systems Laboratory (ESL) of École Polytechnique Fédérale de Lausanne (EPFL). He completed his Ph.D. in Computer Engineering at Universidad Complutense de Madrid (UCM) in 2024. His research focuses on computer arithmetic, domain-specific accelerators, and RISC-V core customization, with a strong emphasis on energy-efficient and high-performance computing solutions. Key research contributions include the development of the PERCIVAL open-source RISC-V core integrating Posit and Quire arithmetic, energy-efficient MAC units, and the LiveChess2FEN framework for chessboard digitization using CNNs optimized for the Jetson Nano platform. His work bridges hardware design, algorithm optimization, and embedded systems applications. Publications highlight advancements in Posit arithmetic implementation, low-cost approximate computing units, and RISC-V architecture extensions. Current projects explore scientific computing applications of 64-bit Posit arithmetic and energy-efficient wearables through precision optimization. Lead developer of PERCIVAL RISC-V core Co-developer of LiveChess2FEN framework Contributor to IEEE Transactions on Computers and Emerging Topics in Computing
