David Mallasén Quintana

David Mallasén Quintana is a Postdoctoral Researcher in Computer Engineering at the Embedded Systems Laboratory (ESL) of École Polytechnique Fédérale de Lausanne (EPFL). He completed his Ph.D. in Computer Engineering at Universidad Complutense de Madrid (UCM) in 2024. His research focuses on computer arithmetic, domain-specific accelerators, and RISC-V core customization, with a strong emphasis on energy-efficient and high-performance computing solutions.

Key research contributions include the development of the PERCIVAL open-source RISC-V core integrating Posit and Quire arithmetic, energy-efficient MAC units, and the LiveChess2FEN framework for chessboard digitization using CNNs optimized for the Jetson Nano platform. His work bridges hardware design, algorithm optimization, and embedded systems applications.

Publications highlight advancements in Posit arithmetic implementation, low-cost approximate computing units, and RISC-V architecture extensions. Current projects explore scientific computing applications of 64-bit Posit arithmetic and energy-efficient wearables through precision optimization.

• Lead developer of PERCIVAL RISC-V core
• Co-developer of LiveChess2FEN framework
• Contributor to IEEE Transactions on Computers and Emerging Topics in Computing