جست‌وجوی استاد و پژوهشگر

Joe Deviettiمشاهده پروفایل

دانشیار

• Computer Architecture
• Parallel Programming
• Concurrency
• +۴ مورد دیگر

Joseph Devietti is an Associate Professor in the Department of Computer & Information Science at the University of Pennsylvania. His research focuses on improving programmability and performance of multiprocessor systems through architectural and programming model innovations. He actively advises PhD students and has supervised numerous graduates now employed at leading tech companies and academic institutions. Education: PhD (2012), MS (2009) in Computer Science and Engineering from University of Washington; BSE (2006) in Computer Science and BA (2006) in English from University of Pennsylvania. Employment: Associate Professor (2020–present), Assistant Professor (2013–2020) at University of Pennsylvania; Principal Scientist & Co-founder at Cloudseal, Inc. (2018–2020). Devietti’s research spans computer architecture, parallel programming, and deterministic execution. Key areas include cache/memory optimization (prefetching, false sharing repair), GPU programming models (race detection, block-size independence), and hardware-software co-design for concurrency safety. His recent work addresses dynamic runtime prefetch tuning (RPG 2 ), online code layout optimization (OCOLOS), and intelligent BTB prefetching (Twig) for data center applications. His publications from 2024–2017 reveal trends in instruction/cache optimization (2024–2020), GPU determinism (2018–2017), and race detection (2018–2016). Awards include the 2024 Penn Engineering Ford Motor Company Award, Radhia Cousot Best Paper (2018), and IEEE Micro Top Picks recognition (2023, 2009, 2008). Scientific Awards : 2024 Penn Engineering Ford Motor Company Award Radhia Cousot Young Researcher Best Paper Award (SAS 2018) IEEE Micro Top Picks (2023, 2009, 2008) Intel Early Career Faculty Honor Program (2013) Intel Ph.D. Fellowship (2011) Advising : Supervised 15+ PhD/Master’s students with placements at Google, Microsoft, Amazon, NYU, and the United States Naval Academy. Collaborations : Works with industry leaders (NVIDIA, Facebook) and academic institutions (University of Washington, Penn).

Mateo Valero Cortésمشاهده پروفایل

استاد

• Computer Architecture
• High-Performance Computing
• Parallel Computing
• +۳ مورد دیگر

Mateo Valero Cortés is a renowned Professor of Computer Architecture at the Polytechnic University of Catalonia and Director of the Barcelona Supercomputing Center (BSC). He has held academic and leadership roles since 1974, advancing high-performance computing (HPC) and computer architecture research. His work includes pioneering contributions to vector architectures, multithreading, and instruction-level parallelism. Education includes a Telecommunications Engineering degree from the Polytechnic University of Madrid (1974) and a PhD in Telecommunications Engineering from the Polytechnic University of Catalonia (1980). His research spans over 700 publications, focusing on HPC systems, parallel computing, and supercomputing infrastructure. Key research interests include vector processing, super-scalar processors, and task-based programming models. Recent work emphasizes scalable architectures for exascale computing and energy-efficient hardware-software co-design. Notable achievements include the Eckert-Mauchly Prize (highest in computer architecture), Seymour Cray Award, and Charles Babbage Prize. He has led initiatives like the Spanish Supercomputing Network (RES) and PRACE (European HPC partnership). Academic affiliations include the Royal Academy of Engineering of Spain, ACM Fellow, and IEEE Fellow. He has received 13 honorary doctorates and awards such as Mexico’s Order of the Aztec Eagle. Current projects include the Mont-Blanc HPC prototype and ERC-funded research on multi-core chip design. His BSC oversees over 300 researchers and manages MareNostrum supercomputers.

• Computer Architecture
• Reconfigurable Computing
• Network-on-Chip (NoC)
• +۷ مورد دیگر

Ioannis Sourdis is a Full Professor at the Department of Computer Engineering, Chalmers University of Technology, Sweden. His research focuses on computer architecture, reconfigurable computing, network-on-chip (NoC) design, memory systems, and fault-tolerant embedded systems, with applications in biomedical informatics and hardware security. Current projects include EUMMSS (Efficient Uncore Mechanisms for Multicore Space Systems, funded by the Swedish National Space Board) and eProcessor (European Processor Ecosystem, funded by the European Commission). Past initiatives include the DeSyRe project (on-demand system reliability), ECOSCALE (exascale reconfigurable computing), and SHARCS (secure hardware-software architectures). His work spans NoC router design (e.g., FastTrackNoC, DDRNoC), memory compression (MemSZ, L2C), and biomedical security applications (heartbeat-based protocols). He has published extensively in venues like DATE, ICS, PACT, and IEEE Transactions on Networking. Key research areas: Chiplet-based systems , hybrid memory architectures , FPGA acceleration , and real-time stream aggregation .

• Computer Security
• Hardware-Software Co-design
• Confidential Computing
• +۴ مورد دیگر

Frank Piessens is a Full Professor in the Department of Computer Science at KU Leuven's Faculty of Engineering Science, where he leads the Distributed and Secure Software (DistriNet) research group. His research focuses on cutting-edge security challenges at the hardware-software interface. His research interests span: Hardware-software co-design for end-to-end security Confidential computing architectures Microarchitectural side-channel mitigation Secure IoT development Compiler-based security mechanisms Control-flow integrity techniques Recent publications (2024-2025) demonstrate strong focus on: Hardware security cost/performance tradeoffs Processor-level security enhancements (RISC-V, high-end CPUs) IoT device lifecycle security Control-flow leakage prevention Microcontroller IP protection He currently supervises PhD students including M. Bognár and H. Winderix, and leads major research initiatives such as: Hardening confidential computing through vertically integrated system design (2025-2031) Designing secure hardware for software-exploitable attacks (2025-2029) Compiler-based mitigations for microarchitectural side-channels (2023-2027) Security Arms Race at the Hardware-Software Boundary (2020-2025)

Labros Bisdounisمشاهده پروفایل

استاد

• CMOS Circuit Design
• Low-Power Electronics
• Embedded Systems
• +۴ مورد دیگر

Labros Bisdounis is a Professor at the Department of Electrical and Computer Engineering, University of the Peloponnese, Greece. He previously held positions at the Technological Educational Institute of Western Greece, including Associate Professor, Full Professor, and Dean of the School of Technological Applications (2016–2018). He has extensive industry experience as a senior research engineer and project manager at Intracom S.A. (2000–2008), focusing on VLSI circuits and telecom applications. His research interests include CMOS circuit timing/power modeling, low-power/high-speed design, MOSFET modeling, and sensor applications. He has authored over 30 papers with 740+ citations and is an IEEE member. Education: Diploma in Electrical Engineering (1992), University of Patras Ph.D. in Electrical Engineering (1999), University of Patras Research Interests: CMOS circuit timing and power dissipation modeling Deep-submicron/nano-CMOS circuit design MOSFET device modeling Low-power embedded systems and SoC Sensor applications and organic electronics Leadership Roles: Dean of the School of Engineering, University of the Peloponnese (2023–present) Director of Training & Lifelong Learning Centre (2019–2019) Board Member, Hellenic NARIC (2016–2019) Collaborations: Active at the Hellenic Open University as a tutor in Computer Architecture and Digital Systems modules. Co-developed the AETHER framework for pervasive computing and contributed to energy-aware SoC designs for 5 GHz WLANs.

Baibhab Chatterjeeمشاهده پروفایل

استادیار

• Biomedical IoT
• Wireless Implants
• Low-Power Circuits
• +۲ مورد دیگر

Baibhab Chatterjee is an Assistant Professor in Electrical and Computer Engineering at the University of Florida. His research focuses on developing energy-efficient integrated circuits and systems for biomedical IoT applications, neural implants, and secure body area networks. Research interests include ultra-low power circuits for biomedical sensors, novel wireless communication techniques through human tissues, brain-computer interfaces, and hardware security for implantable devices. His lab develops innovative solutions for next-generation healthcare monitoring and intervention systems. Recent publications demonstrate expertise in wireless power transfer for implants, in-memory computing architectures, and communication techniques optimized for the human body environment. The work consistently addresses challenges of miniaturization, power efficiency, and reliability in biomedical systems. Best 3-Minute Thesis Award, IEEE Microwave Week 2020 Best Paper Awards at IEEE CICC and HOST conferences Bilsland and Andrews Fellowships

• Computer Architecture
• Microarchitecture
• Memory Systems
• +۴ مورد دیگر

Rakesh Kumar is an Associate Professor in the Department of Computer Science (IDI) at the Norwegian University of Science and Technology (NTNU) , affiliated with the Computer Architecture Lab (CAL) within the Faculty of Information Technology and Electrical Engineering . Prior to joining NTNU, he held postdoctoral and research associate positions at Uppsala University and the University of Edinburgh, and interned at Intel Barcelona Research Center. Research Interests include improving large-scale datacenter efficiency through microarchitecture and memory system optimizations, hardware/software co-designed processors, dynamic code translation, vectorization, and serverless function execution. His work explores ready-aware instruction scheduling, branch prediction organization, and address translation mechanisms. Scientific Contributions span publications at top-tier conferences like MICRO (2024, 2023, 2018, 2016) HPCA (2020, 2019, 2023, 2022) ASPLOS (2018) DATE (2019, 2021) Journal articles appear in ACM Transactions on Computer Systems and IEEE Computer Architecture Letters . Awards include Intel Spontaneous Level II/Excellence Award (2014) Best Presentation Award at HiPC-SS08 (2008) Best Paper Award at National Conference on High Computing Technologies (2008) Distinguished Artifact Award at MICRO 2023 PhD Supervision involves advising students like Roman Kaspar Brunner, Elias Orrem, and Truls Asheim on topics spanning microarchitecture, vector units, and runahead execution policies.

Greg Stittمشاهده پروفایل

استاد

• Computer Engineering
• Embedded Systems
• Reconfigurable Computing
• +۵ مورد دیگر

Greg Stitt is a Professor in the Department of Electrical and Computer Engineering at the University of Florida, affiliated with the College of Engineering. His research focuses on reconfigurable computing, FPGA acceleration, embedded systems, and compiler design. He has received notable awards including the NSF CAREER Award (2012-2017) and the Undergraduate Teacher of the Year Award (2014). His work emphasizes elastic computing frameworks, intermediate fabrics for FPGA virtualization, and warp processors for dynamic hardware/software partitioning. Education: PhD, Computer Science, University of California-Riverside, 2007 BS, Computer Science, University of California-Riverside, 2000 Research Interests: Reconfigurable computing, FPGAs, GPUs, and their applications in high-performance computing Compiler optimization and synthesis techniques for embedded systems Elastic computing frameworks for heterogeneous systems Approximate computing and energy-efficient architectures Grants & Awards: National Science Foundation (NSF) grants for elastic computing (CNS-0914474) and intermediate fabrics (CNS-1149285) Recognition for contributions to FPGA-based scientific computing tools Teaching: Current courses include Reconfigurable Computing 2 and Digital Design Past course offerings span embedded systems, compiler design, and hardware architecture Labs & Teams: Active research in FPGA acceleration, novel architectures, and security for reconfigurable systems Contributions to the Novo-G scalable reconfigurable supercomputing project

Fan Yaoمشاهده پروفایل

دانشیار

• Computer Architecture
• Hardware Security
• AI Security
• +۵ مورد دیگر

Fan Yao is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Central Florida's College of Engineering and Computer Science. She received her Ph.D. in Computer Engineering from The George Washington University in 2018 and currently leads the Computer Architecture and Systems Research (CASR) lab. Her research focuses on the intersection of computer architecture, security, and machine learning, with particular emphasis on hardware-based security vulnerabilities and defenses. Dr. Yao's research interests span computer architecture, hardware and system security, AI security, energy-efficient computing, and cloud computing. Her work addresses critical security challenges in modern computing systems, particularly focusing on microarchitecture attacks, hardware-based model tampering in deep learning systems, and information leakage threats in emerging non-volatile memory systems. She has developed innovative defense mechanisms against cache timing channels, branch predictor vulnerabilities, and GPU-based side channels. Her recent publications demonstrate a strong focus on AI security (particularly Deep Neural Network vulnerabilities), hardware security (including cache and branch predictor attacks), and secure memory architectures. The research shows an evolution from traditional computer architecture topics toward the security implications of AI hardware and emerging memory technologies, with increasing emphasis on practical attacks and defenses in real-world systems. NSF GW I-Corps Site Grant Award, 2018 Best Dissertation Award, GWU, 2018 The Norris & Betty Hekimian Engineering Endowment Fellowship, GWU, 2017 Top Picks in Hardware and Embedded Security, 2019 NSF CAREER project award, 2024 Dr. Yao currently leads multiple NSF-funded research projects including 'Understanding and Taming Deterministic Model Bit Flip Attacks in Deep Neural Networks' (NSF SaTC, 2020-2023), 'Towards Secure-By-Design Integration of Emerging Non-Volatile Memory in Future System' (NSF CNS, 2020-2023), and 'Architecting Secure-by-Design Memristor-Based Memories' (NSF CNS, 2019-2022). She has successfully mentored numerous PhD students, many of whom appear as first authors on top-tier conference publications, demonstrating her commitment to graduate education and research mentorship. As the leader of the CASR lab, Dr. Yao oversees a vibrant research group focused on building secure-by-design, efficient, and advanced future systems through novel techniques spanning hardware, computer architecture, and systems. The lab actively publishes at top computer architecture and security conferences including ISCA, MICRO, HPCA, IEEE S&P, and USENIX Security, with multiple papers accepted to these venues annually. The group has developed several influential tools and frameworks for security analysis, including proof-of-concept code for BranchSpec exploits that has been widely cited in the hardware security community.

Ashish Venkatمشاهده پروفایل

دانشیار

• Computer Architecture
• Compilers
• Computer Security
• +۱۲ مورد دیگر

Ashish Venkat is an Associate Professor in the Department of Computer Science at the University of Virginia, part of the School of Engineering and Applied Science. He holds a Ph.D. from UC San Diego and has established himself as a leading researcher in computer architecture, compilers, and computer security. Research Interests: His research focuses on cross-disciplinary hardware and software techniques to build secure, high-performance computing systems. He investigates robust exploit mitigations that maintain energy efficiency and programmability, with a particular emphasis on speculative execution, memory safety, hardware security, and privacy-preserving computing. He also explores the application of machine learning to detect security threats and model execution behavior. Publication Trends: His recent publications (2020–2025) demonstrate a strong focus on hardware-based security, particularly microarchitectural vulnerabilities (e.g., micro-op cache attacks), memory safety via microcode capabilities, and secure accelerators for bioinformatics. There is a consistent trend of publishing in top-tier venues like ISCA, MICRO, IEEE S&P, and USENIX Security, often featuring novel hardware/software co-design solutions. Scientific Awards: NSF CAREER Award (2023) NSF CRII Award (2018) IEEE Micro Top Pick (2019) IEEE Design & Test Top Pick (2020, 2021) HPCA Best Paper Runner-Up (2019) DATE Best Paper Nominee (2023) UVA Research Achievement Award (2023) ISCA Prolific Author of the Decade (2013–2022) Advising and Grants: He actively mentors graduate and undergraduate students, many of whom have pursued advanced degrees or joined leading tech companies. He has secured significant funding as PI or co-PI from NSF, DARPA, SRC, and Intel, including a $4.9M DARPA HERCULES grant and an NSF CAREER award. His projects focus on holistic security solutions, speculative optimization, and privacy-preserving machine learning frameworks. Labs and Teams: He leads a research group focused on secure and efficient computing systems, collaborating with researchers at institutions like UC San Diego, UC Riverside, and UC Irvine, as well as industry partners including Intel and IBM.

Yale N. Pattمشاهده پروفایل

استاد

• Computer Architecture
• Systems and Networking
• High Performance Computing
• +۳ مورد دیگر

Yale N. Patt serves as Professor of Electrical and Computer Engineering, holding the Ernest Cockrell, Jr. Centennial Chair in Engineering and recognized as a University Distinguished Teaching Professor at The University of Texas at Austin's Cockrell School of Engineering. His academic career spans decades with continuous teaching activity through Fall 2024 and Spring 2025 semesters. Professor Patt's research focuses on computer architecture and high-performance computing systems, specifically targeting innovations five to ten years beyond current industry capabilities. His philosophy emphasizes producing foundational knowledge for future technology development while educating students who will design tomorrow's computing systems. His work spans computer architecture, systems and networking, with particular focus on high performance substrate and microarchitecture design. His research group HPS (High Performance Systems) has made significant contributions to memory systems, branch prediction, and parallel computing architectures. Professor Patt's publications reveal consistent focus on fundamental computer architecture challenges, particularly addressing memory systems, branch prediction mechanisms, and performance optimization techniques that enable future computing systems. His work bridges theoretical innovation with practical application requirements. His exceptional contributions have been recognized with numerous prestigious awards: 2014 - Member, National Academy of Engineering 1996 - IEEE/ACM Eckert-Mauchly Award 2016 - Benjamin Franklin Medal, Franklin Institute 2000 - ACM Karl V. Karlstrom Outstanding Educator Award 1995 - IEEE Emanuel R. Piore Award 2013 - IEEE Harry H. Goode Award 1999 - IEEE Wallace W. McDowell Award 2011 - IEEE B. Ramakrishna Rau Award 2005 - IEEE Charles Babbage Award 2017 - Friar Centennial Teaching Fellowship (the highest teaching award at UT Austin, with recognition as the only Engineering professor to win it in the last 25 years) Professor Patt has mentored numerous PhD students throughout his career and co-authored the influential textbook 'Introduction to Computing Systems: From Bits and Gates to C and Beyond' (3rd edition, 2019). His teaching philosophy emphasizes deep understanding of computing fundamentals, reflected in his 'Ten Commandments for good teaching.' He has developed foundational courses including EE460N (Computer Architecture), EE306, and EE382N.19 (Microarchitecture), with teaching records dating back to at least 2000. He leads the High Performance Systems research group, which continues to advance computer architecture research while training the next generation of computer engineers. Workshops celebrating his 75th birthday in 2014 ('Yale@75') and 80th birthday in 2019 ('Yale:80-in-2019') demonstrate the global respect he has earned in the computer architecture community.

Mark Oskinمشاهده پروفایل

استاد مدعو

• Computer Architecture
• Parallel Computing
• Graph Processing
• +۱۲ مورد دیگر

Mark Oskin is an Adjunct Professor at the School of Computer Science and Engineering , University of Washington , focusing on Software & Hardware Systems . He leads the Sampa Group and collaborates on projects like HammerBlade and BlackParrot. University: University of Washington School: School of Computer Science and Engineering Department: Department of Electrical & Computer Engineering His research spans Computer Architecture , Parallel Computing , and Graph Processing , with additional expertise in Quantum Computing , Open Source Hardware , and Distributed Shared Memory . Ongoing work includes custom manycore devices for graph execution and open-source RISC-V designs. Past projects like Grappa and WaveScalar advanced distributed memory and dataflow execution. Recent publications include BlackParrot: An Agile Open Source RISC-V Multicore for Accelerator SoCs (IEEE Micro 2020) and Perceptual Compression of Video Storage and Processing Systems (SoCC 2019), reflecting trends in hardware-software co-design, quantum systems, and energy-efficient video processing. Best Paper Award , USENIX ATC 2015 IEEE Micro Top Picks , 2009 Mark has advised numerous students, including Amrita Mazumdar (IoT video compression startup), Brandon Lucia (CMU), and Steve Swanson (UC San Diego). He co-founded Corensic, a startup exploring deterministic multithreaded execution.

Alberto Rosمشاهده پروفایل

استاد

• Computer Architecture
• Parallel Processing
• Multicore Processors
• +۵ مورد دیگر

Alberto Ros is a Full Professor at the University of Murcia , Spain, in the Computer Engineering Department (DITEC) . His work focuses on cache coherence , memory hierarchy designs , memory consistency , and processor microarchitecture , with over 100 peer-reviewed publications. Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh , and held postdoctoral positions at the Technical University of Valencia and Uppsala University . He is an IEEE Senior Member . Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance. Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols. Scientific awards : Inducted into the MICRO Hall of Fame ISCA Hall of Fame 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS) Winner, ML-based Data Prefetching Competition Winner, 1st Instruction Prefetching Championship IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable) Best paper awards at HiPC'16, FORTE'16 Honorable mention at HPCA'24 Nomination at ISCA'22 Grants as Principal Investigator include ERC Proof of Concept (2023) ERC Consolidator (2018) Europe Excellence (2018) Seneca Foundation, Young Leaders in Research (2014) . Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.

Franz Fuchsمشاهده پروفایل

پژوهشگر ارشد

• Computer Architecture
• Cybersecurity
• Hardware Security
• +۳ مورد دیگر

Franz Fuchs is a Research Fellow at the Department of Computer Science and Technology (University of Cambridge), working on cutting-edge topics in computer architecture and security. His research focuses on hardware security mechanisms, processor architecture design, and formal verification of microarchitectures. He is affiliated with the Computer Architecture Group and contributes to projects such as the Toooba out-of-order CHERI-RISC-V microprocessor. Fuchs collaborates on developing novel approaches to mitigate transient-execution attacks and improve CPU testing methodologies. His work bridges theoretical computer science principles with practical hardware implementations. He holds a position in the University’s William Gates Building and can be reached at franz.fuchs@cl.cam.ac.uk . His research aligns with the department’s initiatives in secure computing and advanced microprocessor design.

• Computer Architecture
• Microarchitecture
• Compilers
• +۷ مورد دیگر

Antonio Maria Gonzalez Colas is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture within the Faculty of Computer Science of Barcelona (FIB). He leads the ARCO research group focused on Microarchitecture and Compilers and is actively engaged in high-impact research in computer architecture, GPUs, and energy-efficient computing. His collaborations extend to the Barcelona Supercomputing Center and various national and European research initiatives. Research Interests: His primary research areas include computer architecture, microarchitecture, compilers, GPUs, and processor design. He focuses on energy-efficient computing, deep neural network (DNN) accelerators, GPU simulation and optimization, memory systems, and architectural support for machine learning and autonomous systems. His work often integrates compiler techniques with hardware design for performance and efficiency. Scientific Production Trends: His recent publications demonstrate a strong focus on energy-efficient hardware for AI workloads, particularly DNN and speech recognition acceleration, GPU architectural innovations, memory optimization, and real-time rendering. He frequently publishes in top-tier venues such as ISCA, MICRO, HPCA, and IEEE/ACM journals. ICREA Academia Award 2024 HiPEAC 2024 Paper Award ACM Senior Member (2020) Advising and Grants: He has advised numerous PhD students whose theses cover topics like energy-efficient architectures for autonomous driving, speech recognition, and neural networks. He leads competitive R&D projects, including an ERC Advanced Grant and projects funded by the Spanish National Program and the ICREA Academia program, focusing on domain-specific architectures and cognitive computing units. Labs and Teams: He is the principal investigator of the ARCO (Microarchitecture and Compilers) research group at UPC, a leading team in computer architecture research in Spain. The group is part of a larger collaborative network within UPC and with international partners.