Alberto Ros

Alberto Ros is a Full Professor at the University of Murcia, Spain, in the Computer Engineering Department (DITEC). His work focuses on cache coherence, memory hierarchy designs, memory consistency, and processor microarchitecture, with over 100 peer-reviewed publications.

Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh, and held postdoctoral positions at the Technical University of Valencia and Uppsala University. He is an IEEE Senior Member.

Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance.

Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols.

Scientific awards: Inducted into the

• MICRO Hall of Fame
• ISCA Hall of Fame
• 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS)
• Winner, ML-based Data Prefetching Competition
• Winner, 1st Instruction Prefetching Championship
• IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable)
• Best paper awards at HiPC'16, FORTE'16
• Honorable mention at HPCA'24
• Nomination at ISCA'22

Grants as Principal Investigator include

• ERC Proof of Concept (2023)
• ERC Consolidator (2018)
• Europe Excellence (2018)
• Seneca Foundation, Young Leaders in Research (2014)

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Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.