Kaiyuan Yang is an Associate Professor in the Department of Electrical and Computer Engineering at Rice University, leading the Secure and Intelligent Micro-Systems (SIMS) Lab. His research focuses on low-power integrated circuits and bioelectronic implants for applications like the Internet of Everything and medical devices. He holds a B.S. from Tsinghua University (2012) and M.S./Ph.D. degrees from the University of Michigan (2017). Research Interests: Low-power digital/analog/mixed-signal systems Bioelectronics and implantable devices Hardware security and PUF design Mixed-signal computing and emerging materials Recent work emphasizes magnetoelectric-powered implants, secure backscatter communication, and in-memory computing architectures. His publications span top venues like IEEE ISSCC, IEDM, and ACM MobiCom. Awards: 2022 NSF CAREER Award 2022 IEEE Top Picks in Hardware Security 2016 IEEE SSCS Predoctoral Achievement Award Dr. Yang serves on editorial boards for IEEE TVLSI and program committees for ISSCC/CICC. His lab develops miniature, secure, and energy-efficient systems for healthcare and IoT applications.
Lloyd W. Massengill is a Professor of Electrical and Computer Engineering at Vanderbilt University's School of Engineering. His research focuses on radiation-hardened circuit design, simulation of radiation effects on microelectronics, soft error analysis, and analog circuit design. He holds a Ph.D., M.S., and B.S. in Electrical Engineering from North Carolina State University. Dr. Massengill's work addresses critical challenges in semiconductor reliability under ionizing radiation, including total ionizing dose (TID) effects, single-event upsets (SEUs), and transient analysis in advanced FinFET technologies. His contributions span radiation-hardened analog-to-digital converters, mitigation techniques for soft errors, and advanced node radiation testing methodologies. His scientific achievements include receiving the Outstanding Conference Paper Award at the 2024 IEEE Nuclear and Space Radiation Effects Conference and the 2014 counterpart. His research has been published in over 50 peer-reviewed articles, emphasizing radiation effects in nanoscale circuits and space electronics. Notable projects include CubeSat-based real-time soft error measurements in low Earth orbits and the RadFxSat flight campaign for characterizing commercial electronics in space. His work bridges semiconductor physics with practical applications in aerospace and high-reliability systems. His educational background includes degrees from North Carolina State University, demonstrating a deep technical foundation in electrical engineering. While no specific grants or advising details are listed here, his prolific publication record underscores his leadership in radiation effects research.
Rajkumar Sarma is a Research Fellow at the Department of Computer Science & Information Systems at Lero – the Research Ireland Centre for Software, University of Limerick. His work focuses on hardware design, VLSI systems, and optimization techniques for digital circuits. He specializes in areas such as low-power architectures, floating-point arithmetic, and evolutionary algorithms for automated design. His research emphasizes hardware-software co-design, reliability analysis under PVT (Process, Voltage, Temperature) variations, and efficient implementations of multiply-accumulate (MAC) units critical to digital signal processing and image processing applications. Key technical contributions include the development of the UCM algorithm for delay optimization, grammatical evolution for synthesizable HDL code generation, and novel approaches to reduce power consumption in MAC architectures. His work bridges theoretical algorithmic innovation with practical VLSI implementation challenges, addressing both performance and reliability under extreme operating conditions. Rajkumar’s publications span 2012–2025, with a strong focus on digital circuit design, including hybrid adders, low-power flip-flop implementations, and quantum gate-based reversible circuits. His research also extends to reliability analysis of electronic components like multi-layer ceramic capacitors. He has utilized advanced simulation tools such as Cadence ADE-XL for accelerated PVT analysis, demonstrating expertise in both computational modeling and hardware validation. While no specific awards or grants are listed, his extensive publication record reflects sustained engagement with cutting-edge challenges in computer architecture and VLSI systems design.
Prof. Hans-Joachim Wunderlich is a Professor at the University of Stuttgart's Institute of Computer Architecture and Computer Engineering, within the Faculty of Computer Science, Electrical Engineering, and Information Technology. His research focuses on hardware reliability, fault tolerance, and testing methodologies for VLSI circuits and embedded systems. He specializes in areas such as delay fault testing under PVT variability, approximate communication, and aging-aware design. Key research interests include robust testing techniques for small delay faults, error-tolerant communication protocols (e.g., RAPPER and Gray code-based approaches), and GPU-accelerated simulation of faults. His work addresses challenges in functional safety, interconnect reliability, and securing reconfigurable architectures against security violations. He explores energy-efficient iterative solvers for approximate computing environments and develops methods for predicting device aging and early life failures. Prof. Wunderlich’s contributions span academic and industrial applications, with a focus on real-time systems and dependable multi-processor systems-on-chip (MPSoCs). His research integrates formal verification, machine learning for defect detection, and hybrid protection schemes for reconfigurable scan networks. Recent work emphasizes stress-aware testing strategies and optimization of sensor data streaming in resource-constrained environments.
Shubin Liu is a researcher specializing in microelectronics, integrated circuits, and analog circuit design. His work focuses on advanced ADC architectures (e.g., pipelined SAR, time-interleaved, noise-shaping), phase-locked loops (PLL), and sensor readout systems for MEMS and biomedical applications. Recent publications highlight collaborations with Zhangming Zhu and colleagues on high-speed, low-power, and PVT-robust designs. Research interests span Analog-to-digital conversion Low-power RF front-ends Calibration techniques High-frequency oscillators Biopotential amplifiers Time-interleaved ADCs His 15 most recent articles (2023-2025) explore power-efficient ADCs, jitter reduction in PLLs, and sensor interfaces, with keywords including Electronics, Integrated Circuits, Signal Processing, and Microelectronics. Notable subfields: SAR ADCs, Time-Domain Interpolation, Capacitor Mismatch Compensation, and IoT-optimized designs. Shubin Liu’s work is published in journals like IEEE Journal of Solid-State Circuits , Microelectronics Journal , and conferences such as CICC and ISSCC, reflecting his active engagement in cutting-edge analog and mixed-signal research.
Michael Pehl is an Associate Professor at the Chair of Security in Information Technology at Technische Universität München (TUM), where he leads the Hardware-Intrinsic Security research group. His work focuses on Physical Unclonable Functions (PUFs), side-channel analysis, and secure hardware design. His primary research interests include Physical Unclonable Functions, Hardware Security, Side-Channel Analysis, Fault Injection Attacks, Post-Quantum Cryptography, Secure Hardware Design, and Trusted Electronics. Pehl has developed significant expertise in PUF security mechanisms, with particular emphasis on countermeasures against side-channel attacks and entropy optimization in security primitives. His recent publications demonstrate strong trends in hardware security, particularly in PUF architectures (oscillator-based, resistor-based, memristor-based), side-channel countermeasures, and entropy analysis. The research spans both theoretical foundations and practical implementations for secure embedded systems. Kurt-Fischer Prize (2013) Outstanding Reviewer Award at ICASSP 2022 Outstanding Reviewer Award at DATE 2024 Pehl has secured substantial research funding through multiple high-profile projects including STAMPS-PLUS (DFG), Edu4Chip (EU), APRIORI (BMBF), and VE-FIDES (BMBF). He serves as an Associated Editor for IEEE Transactions on Information Forensics & Security and has held leadership roles in major conferences including Program Co-Chair of COSADE 2023. His research group actively collaborates with industry partners and contributes to TUM's Center of Competence for Design of Electronic Circuits and Systems (DECS). Pehl's laboratory focuses on Hardware-Intrinsic Security research, with specialized facilities for PUF evaluation, side-channel analysis, and fault injection testing. The team develops innovative security primitives for embedded systems and IoT devices, with particular emphasis on post-quantum security solutions.
Christoph Frisch is a researcher at the Chair of Information Security at the Technical University of Munich , focusing on Physical Unclonable Functions (PUFs) and their applications in hardware security. His work explores the intersection of coding theory, information theory, and secure implementation of cryptographic primitives. Current research emphasis on entropy-area trade-offs in quantization schemes for PUFs Contributions to reliability enhancement of security primitives and min-entropy estimation Active in hardware reverse engineering and side-channel attack countermeasures His publications reveal a strong focus on IoT security and post-quantum cryptography , with recent work addressing memristor-based PUFs and polar decoder implementations. No scientific awards are mentioned in the provided text. Teaching activities include delivering Lecture Series on System Security and Applied Cryptology courses since 2017, indicating a dual role in research and education.
Carl Philipp Riehm is a Research Assistant at the Chair of Circuit Design, Technical University of Munich (TUM), working under Prof. Ralf Brederlow since July 2020. His role involves research in circuit design and hardware security, with a focus on analog and mixed-signal systems. His educational background includes: Bachelor of Science in Electrical Engineering, Technical University of Berlin (2017) Degree in Sound Engineering, University of the Arts Berlin (2018) Master of Science in Electrical Engineering and Information Technology, Technical University of Munich (2020) Riehm's research centers on hardware security, particularly Physical Unclonable Functions (PUFs) for tamper protection in embedded systems. He is developing enhanced mechanical stress sensors for copy protection. His work spans analog circuit design, sensor systems, and embedded security, aiming to create resilient security primitives against environmental variations. His 2023 publication on resistor-based PUFs robust to PVT variations exemplifies his focus on practical hardware security solutions for resource-constrained devices. This research contributes to the field by addressing reliability challenges in real-world deployments. At TUM, Riehm participates in teaching laboratory courses and seminars. He also brings industry experience from his student employment at Texas Instruments.
Yan Zhu is a faculty member at the University of Macau , affiliated with the Analog and Mixed Signal VLSI Laboratory within the Faculty of Science and Technology. She has a strong research focus on high-performance analog and mixed-signal integrated circuits, particularly in data conversion and low-power design. Her research interests include: Analog and Mixed-Signal VLSI Design High-Speed Data Converters (ADCs) Noise-Shaping and Time-Domain Circuits PVT-Robust and Low-Power Circuit Techniques Compute-in-Memory and AI Hardware Acceleration The recent publications of Yan Zhu demonstrate a clear trend toward advanced ADC architectures such as time-interleaved, pipelined-SAR, and time-domain converters, with a strong emphasis on calibration, linearity, and energy efficiency. Her work frequently appears in top-tier journals like IEEE JSSC and conferences like ISSCC and CICC, indicating leadership in the field of analog circuit design. There is also a growing focus on machine learning hardware, particularly analog compute-in-memory systems for edge AI applications. No scientific awards or honors are mentioned in the provided text. Yan Zhu has made significant contributions through collaborative research, particularly with Chi-Hang Chan and Rui Paulo Martins , and has been involved in numerous projects related to ADC calibration, metastability, and high-speed sampling. While specific grant details are not listed, the volume and quality of publications suggest active funding support. She has not listed any advisees in the provided data. She is a core contributor to the Analog and Mixed Signal VLSI Laboratory at the University of Macau, where her team focuses on cutting-edge IC design for communication, sensing, and artificial intelligence applications.
Sybille Hellebrand is a Professor and Head of the Data Technology (DATE) department at the University of Paderborn, within the Faculty of Electrical Engineering, Computer Science and Mathematics. She leads research in testing methodologies, fault tolerance, and reliability engineering. Her work focuses on advanced testing techniques for nanoelectronic systems, including BIST (Built-In Self-Test), delay fault analysis, and interconnect reliability under process variations. Key research areas include: Testing and diagnosis of electronic systems Robust testing under PVT (Process-Voltage-Temperature) variability Functional safety of interconnects Approximate communication for error-tolerant systems Hardware fault modeling and simulation Recent publications emphasize advancements in storage-based BIST optimization, defect vs. fault coverage analysis, and cross-talk delay modeling using polynomial regression. She has contributed to international conferences such as European Test Symposium (ETS), IEEE Latin American Test Symposium (LATS), and International Symposium of EDA (ISEDA). Teaching responsibilities include courses on systems engineering, quality assurance in microelectronics, and algorithms for test and diagnosis of systems-on-chip. Her work aligns with emerging challenges in nanoelectronics, including reliability under variations and fault-tolerant communication. No specific awards or grants are listed in the provided texts, but her extensive publication record underscores her leadership in testing and reliability research. The DATE lab at Paderborn University serves as a core research hub for her activities.
Dr. Saraju P. Mohanty is a Professor in the Department of Computer Science and Engineering at the University of North Texas (UNT), where he leads the Smart Electronic Systems Laboratory (SESL). He holds honorary and adjunct positions at IIIT-Naya Raipur, MNIT Jaipur, and Oriental University, Indore, in India. Education: Ph.D. in Computer Science and Engineering, University of South Florida (USF), 2003 Masters in Systems Science and Automation (AI), Indian Institute of Science (IISc), 1999 B.E. in Electrical Engineering (Honors), College of Engineering and Technology, Bhubaneswar (OUAT), 1995 Dr. Mohanty's research is centered on Smart Electronic Systems, with a strong focus on IoT, VLSI, hardware security, and healthcare applications. His work integrates machine learning, embedded systems, and nanoelectronics to develop secure and efficient solutions for smart cities, agriculture, and medical devices. He has authored over 550 peer-reviewed publications and five books, including a PROSE Award-winning textbook. His recent publications reflect a growing emphasis on AI-driven solutions for synthetic media detection, smart farming, driver monitoring, and personalized health. These works demonstrate a trend toward intelligent, edge-based systems that leverage sensor data and lightweight AI for real-time decision-making. Scientific Awards and Honors: Fulbright Specialist Award (2021) IEEE Consumer Electronics Society Outstanding Service Award (2020) IEEE-CS-TCVLSI Distinguished Leadership Award (2018) PROSE Award for Best Textbook (2016) Top 2% Scientist globally (PLOS Biology, 2019–2022) Multiple Best Paper and Best Poster Awards UNT Toulouse Scholars Award (2016–2017) President’s Scout Award, India (1988) Dr. Mohanty has supervised 3 postdocs, 18 Ph.D. students, 29 M.S. theses, and over 40 undergraduate research projects. Eleven of his advisees have received outstanding student awards. He has received multiple UNT Provost’s Thank a Teacher and Honors Day recognitions. His research has been funded by NSF, SRC, US Air Force, NIDILRR, and Mission Innovation. He has held key editorial roles, including Editor-in-Chief of IEEE Consumer Electronics Magazine and founding EiC of IEEE VLSI Circuits and Systems Letter. He is actively involved in IEEE leadership and conference organization, serving on steering committees for IEEE-iSES, ISVLSI, and OCIT. Laboratories and Teams: He directs the Smart Electronic Systems Laboratory (SESL) at UNT, which focuses on cutting-edge research in IoT, edge computing, hardware security, and smart healthcare. The lab fosters interdisciplinary collaboration and has produced numerous award-winning student projects and publications.
