Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Helen Xu is an Assistant Professor at Georgia Tech's School of Computational Science and Engineering (College of Computing). She holds a Ph.D. from MIT (2022) under Charles E. Leiserson and was a Grace Hopper Postdoctoral Fellow at Lawrence Berkeley National Lab (2022). Her research focuses on parallel algorithms, cache-efficient data structures, and high-performance computing. Xu has interned at Microsoft Research, NVIDIA Research, and Sandia National Laboratories, and her work has been supported by prestigious fellowships including the National Physical Sciences Consortium and Chateaubriand awards. **Education**: Ph.D., Computer Science, MIT, 2022 Postdoctoral Research, Lawrence Berkeley National Lab (2022) **Research Interests**: Parallel and cache-friendly algorithms Dynamic graph and data structure optimization Algorithm performance engineering Sparse matrix/tensor operations **Awards**: Grace Hopper Postdoctoral Scholar (2022), Best Artifact Award (PPoPP 2024), National Physical Sciences Consortium Fellowship, Chateaubriand Fellowship. **Advising & Teaching**: Advises PhD/M.S. students in parallel computing and high-performance systems. Teaches courses like CSE 6220 (Introduction to HPC) and CSE 6230 (HPC Tools). Supervised MIT M.Eng. projects on BP-Trees and parallel prefix sums. **Labs/Teams**: Active in Georgia Tech's High-Performance Computing community, collaborating with researchers like Aydın Buluç and Prashant Pandey on graph containers and dynamic data structures.
David I. August is a Professor of Computer Science at Princeton University, affiliated with the Department of Electrical Engineering. He earned his Ph.D. from the University of Illinois at Urbana-Champaign in 2000. His research focuses on compilers and computer architecture, emphasizing synergistic design between compilers and microarchitecture. He leads the Liberty Research Group, which explores topics such as automatic parallelization, memory profiling, and speculative execution. August joined Princeton in 1999 as a lecturer, advancing to full professor in 2012. He has served as program chair for MICRO 2009 and on committees for ISCA, PLDI, and ASPLOS. His notable accolades include the IEEE Fellow designation, Best Paper Awards at PLDI and CGO, and teaching awards from Princeton's School of Engineering. His work spans compiler optimizations, hardware-software co-design, and security architectures like TrustGuard. Recent research includes GPU scheduling (GhOST), memory profiling frameworks (PROMPT), and instruction prefetching (PDIP). He advises over 20 graduate students, many now leading roles at tech companies and academia. August teaches courses such as COS-126 (Intro to CS), COS-375 (Computer Architecture), and graduate seminars. His projects often bridge theory and practice, with tools like NOELLE and Liberty Research Group initiatives advancing compiler infrastructure and parallelism extraction.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
Xiaoning Ding is an Associate Professor in the Department of Computer Science at New Jersey Institute of Technology (NJIT). His research focuses on virtualization, multicore computing, cloud infrastructure optimization, and mobile systems. He leads projects addressing challenges in nested virtualization, memory management, and cache conflicts in distributed and cloud environments. Key research interests include optimizing task scheduling in cloud VMs, reducing TLB misses through huge page strategies, and mitigating interference in multi-tenant GPU clouds. His work on page placement mechanisms and dynamic page coalescing aims to enhance virtualized cloud performance. Ding has received federal funding, including an NSF grant for virtualization research in heterogeneous memory hierarchies (2016–2019). His research outputs span over 74 publications, with notable contributions in EuroSys, IEEE Transactions, and conferences like PACT. Media coverage highlights his studies on cloud computing and collaborative mobile systems, such as parking assignment algorithms. Beyond technical contributions, Ding advises students in interdisciplinary projects, exemplified by collaborations with Applied Math majors on cloud computing challenges.
Charles E. Leiserson is a Professor of Computer Science and Engineering at MIT, holding the Edwin Sibley Webster Professorship in Electrical Engineering and Computer Science. He leads the Supertech Research Group and is Faculty Director of the MIT-Air Force AI Accelerator. His work focuses on parallel computing, performance engineering, and algorithms. Leiserson is renowned for co-authoring the foundational textbook Introduction to Algorithms , widely used in computer science education globally. He has pioneered technologies like the Cilk multithreaded programming language and contributed to supercomputing architectures such as the Connection Machine CM-5. His research bridges theoretical computer science with practical applications, emphasizing cache-oblivious algorithms and compiler optimizations. Leiserson has received multiple awards for his academic contributions and educational impact, including the ACM-IEEE Ken Kennedy Award and Margaret MacVicar Fellow distinction at MIT. Education: B.S., Yale University, 1975 Ph.D., Carnegie Mellon University, 1981 Research Interests: Leiserson’s work addresses performance engineering challenges in post-Moore’s Law computing. His group develops algorithms, software systems, and hardware strategies for scalable parallelism. Key areas include parallel programming frameworks (e.g., OpenCilk), cache-aware algorithms, and compiler optimizations. He emphasizes making parallel computing accessible to mainstream programmers through tools like Cilk and educational initiatives such as MIT’s Software Performance Engineering course. Projects & Leadership: Leiserson leads the Supertech Research Group and contributed to the Cilk Arts Inc. venture, acquired by Intel. He chairs the MIT Undergraduate Practice Opportunities Program (UPOP) and teaches courses on algorithms and discrete mathematics. His leadership workshops for faculty have educated hundreds worldwide on team management in academia. Awards & Recognition: 2014 ACM-IEEE Ken Kennedy Award IEEE Taylor L. Booth Education Award ACM Paris Kanellakis Theory and Practice Award Member of the National Academy of Engineering Labs & Teams: Active in MIT’s CSAIL, Leiserson collaborates through the Supertech Group and Theory of Computation communities. His current projects include Tapir compiler infrastructure, graph neural network applications for anti-money laundering, and deterministic parallel scheduling algorithms.
Arthur F Witulski is a Research Professor of Electrical Engineering at Vanderbilt University's School of Engineering. He specializes in radiation effects on electronic power semiconductor devices and systems, focusing on radiation reliability in aerospace and nuclear environments. His research addresses challenges in satellites, robotics, and high-reliability power electronics. Education: PhD, MS, and BS in Electrical Engineering from the University of Colorado. Research Interests include radiation hardening of power electronics, semiconductor reliability under ionizing environments, and system-level modeling of radiation effects. His work spans energy systems, nano-materials, and risk mitigation strategies for complex engineering projects. Key contributions include developing models for SiC power device failures, Bayesian assurance frameworks for space systems, and methodologies linking component-level testing to system reliability. His recent articles emphasize single-event effects in advanced semiconductors and radiation tolerance in commercial-off-the-shelf (COTS) components. Witulski has pioneered radiation assurance tools for small satellites and robotic systems, emphasizing probabilistic modeling and fault-tolerant designs. His work integrates theoretical physics with practical engineering solutions for harsh radiation environments.
Dwight Makaroff is a Professor in the Department of Computer Science at the University of Saskatchewan . He leads the DISCUS research group , focusing on distributed systems, networking, and performance analysis. Makaroff holds a Ph.D. from the University of British Columbia (1998), an M.Sc. (1988), and a B.Comm. (1985) from the University of Saskatchewan. Research Interests: Distributed Data Processing & Hadoop Network Support for Multiplayer Games Information-Centric Networking Energy Efficiency in Mobile Devices Multicore Architectures Wireless Network Security Sensor Networks & Data Aggregation Teaching: Courses include Operating Systems Principles , Topics in Parallel & Distributed Systems , and advanced systems courses. He coordinated the ACM ICPC programming contest teams for over a decade. Committees: Graduate Committee Chair (2013-2015) University Council Member (2006-2014) Program Committee roles at IEEE/ACM conferences (IPCCC, CASCON, etc.) Recent Research Highlights: IoT security via blockchain Wearable device communication challenges Caching strategies for information-centric networks
Ravi Reddy Manumachu is an Assistant Professor in the School of Computer Science at University College Dublin (UCD), Ireland. He holds a B.Tech from IIT Madras (1997) and a PhD in Computer Science from UCD (2005), specializing in high-performance heterogeneous computing and energy-efficient systems. His research focuses on optimizing performance and energy efficiency in modern heterogeneous platforms like clouds, grids, and supercomputers through novel models and algorithms. Key contributions include functional performance/energy models, energy-prediction frameworks, and extensions like Heterogeneous MPI and ScaLAPACK for heterogeneous clusters. He has published over 69 articles in top journals/conferences, with recent works addressing data transfer energy measurement, scalable allreduce algorithms (SUARA), and portable programming models (OpenH). Professional roles include Assistant Professor at UCD (2023–present), SEAI Research Fellow (2022–2023), and prior industrial experience at Ansys, Siemens, and IONA Technologies. He has certifications in university teaching, GDPR, and research integrity. Languages include English (fluent), Telugu, and Hindi. Research trends emphasize bi-objective optimization (performance-energy), hardware heterogeneity challenges, and scalable communication algorithms for deep learning. His work addresses energy non-proportionality in CPUs and GPU-CPU interactions, with practical solutions for real-world applications like matrix operations and gene sequencing.
François Trahay is a Full Professor in the Computer Science department at Télécom SudParis (Institut Mines-Télécom) and a member of the Benagil Inria team. He leads research in high-performance systems, runtime systems, and performance analysis for HPC and distributed systems. He holds an HDR from Institut Polytechnique de Paris and a PhD from University of Bordeaux (2009). His work includes the EZTrace framework for performance analysis and contributions to storage systems optimization. Education: 2021: Habilitation à Diriger des Recherches (HDR), Institut Polytechnique de Paris 2010: PostDoc at Riken, University of Tokyo 2009: PhD in Computer Science, University of Bordeaux 2006: MS in Computer Science, University of Bordeaux Research focuses on runtime system design, HPC trace analysis, and storage efficiency. Recent projects include PALLAS trace format (IPDPS 2025) and GPU performance prediction (Euro-Par 2024). He advises 4 current PhD students and has supervised 2 former students now in industry. Key contributions include: Co-developer of EZTrace performance analysis framework Co-author of 60+ peer-reviewed papers in top venues (IPDPS, IEEE Cluster, ICPP) Technical leadership in Inria's Benagil team and Samovar Lab
Wen-Ben Jone is an Associate Professor at the University of Cincinnati 's Department of Electrical Engineering & Computing Systems. He previously held positions as Assistant/Associate Professor at New Mexico Institute of Mining and Technology and Visiting Associate/Full Professor at National Chung-Cheng University, Taiwan. His research focuses on VLSI system design, low-power circuits, and fault-tolerant testing methodologies. He has advised over 70 graduate students and authored/co-authored numerous papers in top-tier journals and conferences. Education : PhD: Case Western Reserve University (Computer Engineering, 1987) MS: National Chao-Tung University (Computer Engineering, 1981) BS: National Chao-Tung University (Computer Science, 1979) Research Interests : Reliable VLSI design and testing Low-power and fault-tolerant circuits Many-core processor architectures Parallel computing and debugging tools Awards : 2003 IEEE Donald G. Fink Prize Paper Award 2008 Best Paper Award (International Symposium on Low-Power Electronics) 2012 Best Paper Award (VLSI Design, Automation & Test) Grants : $390k NSF Grant (CCF-0541103) for cache optimization techniques His work emphasizes practical solutions in VLSI testing and reliability, with a focus on low-power strategies and resilient system design.
Jianhui Yue is an Assistant Professor in the Department of Computer Science at Michigan Technological University. His research focuses on computer architecture, operating systems, and system optimization for big data processing. He specializes in memory systems, persistent memory technologies, and hardware acceleration for graph processing and machine learning workloads. His work addresses challenges in optimizing performance, energy efficiency, and reliability in modern computing systems. Key research areas include hybrid memory architectures, in-storage accelerators (e.g., FlashGNN), and crash consistency mechanisms for non-volatile memory. His publications emphasize innovations in cache optimization, NAND flash management, and graph algorithms for dynamic data mining. His recent work (e.g., Cheetah, P3DC) highlights advancements in reducing latency and improving scalability in high-performance computing environments. Dr. Yue’s contributions span hardware-software co-design, with a focus on practical applications of computer architecture principles to real-world systems. His research bridges theoretical concepts with deployable solutions, addressing critical bottlenecks in data-centric computing.
Shervin Hajiamini is an Assistant Professor of the Practice of Computer Science at Vanderbilt University's School of Engineering. He holds a Ph.D. from Washington State University, an M.Sc. from Delft University of Technology, and a B.Sc. from Azad University. His research focuses on green computing, particularly energy efficiency in multi-core systems, including dynamic voltage/frequency scaling (DVFS), voltage-frequency islands (VFI), and task scheduling optimizations. Recent work explores energy efficiency through heuristic algorithms, stochastic models, and dynamic programming frameworks. His articles (2015–2023) emphasize energy-time tradeoffs, cache optimization, and power-aware scheduling in multi-core architectures. No scientific awards are explicitly listed. His advising and grants sections are currently empty. He is affiliated with the School of Engineering's Computer Science department at Vanderbilt University.
Prof. Dr. Jana Giceva is a Professor for Database Systems at the TUM School of Computation, Information and Technology since 2020. Her research bridges database systems with modern computer architecture, focusing on hardware-aware data processing, operating system integration, and efficient execution of big data workloads. She previously held roles at Imperial College London, Microsoft Research, and Oracle Labs. Education: PhD in Computer Science from ETH Zurich (2017) Awards: ERC Starting Grant (2024), ETH Medal (2018), VMware Early Career Faculty Award (2019), Google PhD Fellowship (2014) Her work explores database/operating system co-design , chiplet-aware scheduling , and disaggregated systems programming , with publications covering query optimization, graph data structures, and hardware acceleration. Collaborations with institutions like Imperial College London and ETH Zurich highlight her cross-disciplinary impact. Key Research Themes: Hardware-Software Integration High-Performance Query Execution Asynchronous I/O Optimization Adaptive Runtime Systems
Ziqiang Patrick Huang is an Assistant Professor, Teaching Stream in the Department of Electrical and Computer Engineering at the University of Waterloo, School of Engineering. His research focuses on high-performance and energy-efficient computer architectures, with an emphasis on software/hardware co-design under power and thermal constraints, compiler-assisted performance optimization, and dynamic resource allocation mechanisms. He holds a PhD (2019) and MS (2014) in Electrical and Computer Engineering from Duke University, and a BS (2012) from East China University of Science and Technology. He has taught multiple courses including CS 450/650 (Computer Architecture), ECE 222 (Digital Computers), ECE 250 (Algorithms and Data Structures), ECE 350 (Real-Time Operating Systems), and ECE 621 (Computer Organization) in recent years. His publications span topics such as FPGA NoC design, thermal management in microarchitectures, and dynamic resource allocation strategies. No scientific awards are explicitly listed. He is not currently accepting graduate students.
