Renaud Pacalet is a Researcher at Institut Mines-Télécom – Télécom Paris , affiliated with the Communications and Electronics (Comelec) Department and the System on Chip (LabSoc) research team under the Information Processing and Communication Laboratory (LTCI). His work spans hardware security, embedded systems, and software-defined radio (SDR) architectures. Current Research: Hardware security, side-channel attacks (power, timing, fault injection), RISC-V security analysis using gem5, FPGA scheduling for cloud data centers, and model-driven design methodologies. Past Research: Hardware acceleration for ray tracing, SDR front-end processing, SoC security, and memory bus protection (SecBus project). Teaching: Courses on Digital Systems, Computer Architecture, and Hardware Security at EURECOM, including lab sessions on side-channel attacks and fault analysis. Email: renaud.pacalet@telecom-paris.fr Contact: Télécom ParisTech, Campus SophiaTech, 450 route des Chappes 06410 Biot, France
Mark Oskin is an Adjunct Professor at the School of Computer Science and Engineering , University of Washington , focusing on Software & Hardware Systems . He leads the Sampa Group and collaborates on projects like HammerBlade and BlackParrot. University: University of Washington School: School of Computer Science and Engineering Department: Department of Electrical & Computer Engineering His research spans Computer Architecture , Parallel Computing , and Graph Processing , with additional expertise in Quantum Computing , Open Source Hardware , and Distributed Shared Memory . Ongoing work includes custom manycore devices for graph execution and open-source RISC-V designs. Past projects like Grappa and WaveScalar advanced distributed memory and dataflow execution. Recent publications include BlackParrot: An Agile Open Source RISC-V Multicore for Accelerator SoCs (IEEE Micro 2020) and Perceptual Compression of Video Storage and Processing Systems (SoCC 2019), reflecting trends in hardware-software co-design, quantum systems, and energy-efficient video processing. Best Paper Award , USENIX ATC 2015 IEEE Micro Top Picks , 2009 Mark has advised numerous students, including Amrita Mazumdar (IoT video compression startup), Brandon Lucia (CMU), and Steve Swanson (UC San Diego). He co-founded Corensic, a startup exploring deterministic multithreaded execution.
Greg Stitt is a Professor in the Department of Electrical and Computer Engineering at the University of Florida, affiliated with the College of Engineering. His research focuses on reconfigurable computing, FPGA acceleration, embedded systems, and compiler design. He has received notable awards including the NSF CAREER Award (2012-2017) and the Undergraduate Teacher of the Year Award (2014). His work emphasizes elastic computing frameworks, intermediate fabrics for FPGA virtualization, and warp processors for dynamic hardware/software partitioning. Education: PhD, Computer Science, University of California-Riverside, 2007 BS, Computer Science, University of California-Riverside, 2000 Research Interests: Reconfigurable computing, FPGAs, GPUs, and their applications in high-performance computing Compiler optimization and synthesis techniques for embedded systems Elastic computing frameworks for heterogeneous systems Approximate computing and energy-efficient architectures Grants & Awards: National Science Foundation (NSF) grants for elastic computing (CNS-0914474) and intermediate fabrics (CNS-1149285) Recognition for contributions to FPGA-based scientific computing tools Teaching: Current courses include Reconfigurable Computing 2 and Digital Design Past course offerings span embedded systems, compiler design, and hardware architecture Labs & Teams: Active research in FPGA acceleration, novel architectures, and security for reconfigurable systems Contributions to the Novo-G scalable reconfigurable supercomputing project
Fan Yao is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Central Florida's College of Engineering and Computer Science. She received her Ph.D. in Computer Engineering from The George Washington University in 2018 and currently leads the Computer Architecture and Systems Research (CASR) lab. Her research focuses on the intersection of computer architecture, security, and machine learning, with particular emphasis on hardware-based security vulnerabilities and defenses. Dr. Yao's research interests span computer architecture, hardware and system security, AI security, energy-efficient computing, and cloud computing. Her work addresses critical security challenges in modern computing systems, particularly focusing on microarchitecture attacks, hardware-based model tampering in deep learning systems, and information leakage threats in emerging non-volatile memory systems. She has developed innovative defense mechanisms against cache timing channels, branch predictor vulnerabilities, and GPU-based side channels. Her recent publications demonstrate a strong focus on AI security (particularly Deep Neural Network vulnerabilities), hardware security (including cache and branch predictor attacks), and secure memory architectures. The research shows an evolution from traditional computer architecture topics toward the security implications of AI hardware and emerging memory technologies, with increasing emphasis on practical attacks and defenses in real-world systems. NSF GW I-Corps Site Grant Award, 2018 Best Dissertation Award, GWU, 2018 The Norris & Betty Hekimian Engineering Endowment Fellowship, GWU, 2017 Top Picks in Hardware and Embedded Security, 2019 NSF CAREER project award, 2024 Dr. Yao currently leads multiple NSF-funded research projects including 'Understanding and Taming Deterministic Model Bit Flip Attacks in Deep Neural Networks' (NSF SaTC, 2020-2023), 'Towards Secure-By-Design Integration of Emerging Non-Volatile Memory in Future System' (NSF CNS, 2020-2023), and 'Architecting Secure-by-Design Memristor-Based Memories' (NSF CNS, 2019-2022). She has successfully mentored numerous PhD students, many of whom appear as first authors on top-tier conference publications, demonstrating her commitment to graduate education and research mentorship. As the leader of the CASR lab, Dr. Yao oversees a vibrant research group focused on building secure-by-design, efficient, and advanced future systems through novel techniques spanning hardware, computer architecture, and systems. The lab actively publishes at top computer architecture and security conferences including ISCA, MICRO, HPCA, IEEE S&P, and USENIX Security, with multiple papers accepted to these venues annually. The group has developed several influential tools and frameworks for security analysis, including proof-of-concept code for BranchSpec exploits that has been widely cited in the hardware security community.
Ashish Venkat is an Associate Professor in the Department of Computer Science at the University of Virginia, part of the School of Engineering and Applied Science. He holds a Ph.D. from UC San Diego and has established himself as a leading researcher in computer architecture, compilers, and computer security. Research Interests: His research focuses on cross-disciplinary hardware and software techniques to build secure, high-performance computing systems. He investigates robust exploit mitigations that maintain energy efficiency and programmability, with a particular emphasis on speculative execution, memory safety, hardware security, and privacy-preserving computing. He also explores the application of machine learning to detect security threats and model execution behavior. Publication Trends: His recent publications (2020–2025) demonstrate a strong focus on hardware-based security, particularly microarchitectural vulnerabilities (e.g., micro-op cache attacks), memory safety via microcode capabilities, and secure accelerators for bioinformatics. There is a consistent trend of publishing in top-tier venues like ISCA, MICRO, IEEE S&P, and USENIX Security, often featuring novel hardware/software co-design solutions. Scientific Awards: NSF CAREER Award (2023) NSF CRII Award (2018) IEEE Micro Top Pick (2019) IEEE Design & Test Top Pick (2020, 2021) HPCA Best Paper Runner-Up (2019) DATE Best Paper Nominee (2023) UVA Research Achievement Award (2023) ISCA Prolific Author of the Decade (2013–2022) Advising and Grants: He actively mentors graduate and undergraduate students, many of whom have pursued advanced degrees or joined leading tech companies. He has secured significant funding as PI or co-PI from NSF, DARPA, SRC, and Intel, including a $4.9M DARPA HERCULES grant and an NSF CAREER award. His projects focus on holistic security solutions, speculative optimization, and privacy-preserving machine learning frameworks. Labs and Teams: He leads a research group focused on secure and efficient computing systems, collaborating with researchers at institutions like UC San Diego, UC Riverside, and UC Irvine, as well as industry partners including Intel and IBM.
Yale N. Patt serves as Professor of Electrical and Computer Engineering, holding the Ernest Cockrell, Jr. Centennial Chair in Engineering and recognized as a University Distinguished Teaching Professor at The University of Texas at Austin's Cockrell School of Engineering. His academic career spans decades with continuous teaching activity through Fall 2024 and Spring 2025 semesters. Professor Patt's research focuses on computer architecture and high-performance computing systems, specifically targeting innovations five to ten years beyond current industry capabilities. His philosophy emphasizes producing foundational knowledge for future technology development while educating students who will design tomorrow's computing systems. His work spans computer architecture, systems and networking, with particular focus on high performance substrate and microarchitecture design. His research group HPS (High Performance Systems) has made significant contributions to memory systems, branch prediction, and parallel computing architectures. Professor Patt's publications reveal consistent focus on fundamental computer architecture challenges, particularly addressing memory systems, branch prediction mechanisms, and performance optimization techniques that enable future computing systems. His work bridges theoretical innovation with practical application requirements. His exceptional contributions have been recognized with numerous prestigious awards: 2014 - Member, National Academy of Engineering 1996 - IEEE/ACM Eckert-Mauchly Award 2016 - Benjamin Franklin Medal, Franklin Institute 2000 - ACM Karl V. Karlstrom Outstanding Educator Award 1995 - IEEE Emanuel R. Piore Award 2013 - IEEE Harry H. Goode Award 1999 - IEEE Wallace W. McDowell Award 2011 - IEEE B. Ramakrishna Rau Award 2005 - IEEE Charles Babbage Award 2017 - Friar Centennial Teaching Fellowship (the highest teaching award at UT Austin, with recognition as the only Engineering professor to win it in the last 25 years) Professor Patt has mentored numerous PhD students throughout his career and co-authored the influential textbook 'Introduction to Computing Systems: From Bits and Gates to C and Beyond' (3rd edition, 2019). His teaching philosophy emphasizes deep understanding of computing fundamentals, reflected in his 'Ten Commandments for good teaching.' He has developed foundational courses including EE460N (Computer Architecture), EE306, and EE382N.19 (Microarchitecture), with teaching records dating back to at least 2000. He leads the High Performance Systems research group, which continues to advance computer architecture research while training the next generation of computer engineers. Workshops celebrating his 75th birthday in 2014 ('Yale@75') and 80th birthday in 2019 ('Yale:80-in-2019') demonstrate the global respect he has earned in the computer architecture community.
Alberto Ros is a Full Professor at the University of Murcia , Spain, in the Computer Engineering Department (DITEC) . His work focuses on cache coherence , memory hierarchy designs , memory consistency , and processor microarchitecture , with over 100 peer-reviewed publications. Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh , and held postdoctoral positions at the Technical University of Valencia and Uppsala University . He is an IEEE Senior Member . Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance. Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols. Scientific awards : Inducted into the MICRO Hall of Fame ISCA Hall of Fame 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS) Winner, ML-based Data Prefetching Competition Winner, 1st Instruction Prefetching Championship IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable) Best paper awards at HiPC'16, FORTE'16 Honorable mention at HPCA'24 Nomination at ISCA'22 Grants as Principal Investigator include ERC Proof of Concept (2023) ERC Consolidator (2018) Europe Excellence (2018) Seneca Foundation, Young Leaders in Research (2014) . Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.
Cynthia H. McCollough, Ph.D., is a Professor of Biomedical Engineering and Medical Physics at Mayo Clinic, where she serves as a Consultant in the Department of Radiology. She leads the CT Clinical Innovation Center, focusing on advancing CT imaging technology and clinical applications. Her work emphasizes radiation dose reduction, quantitative material composition analysis (e.g., kidney stones, gout), and optimizing CT protocols for diagnostic accuracy while minimizing patient risk. Dr. McCollough holds leadership roles in national and international organizations, including the NIH Biomedical Imaging Technology Study Section and the American Association of Physicists in Medicine (AAPM). She has received numerous awards, including the Distinguished Investigator Award from Mayo Clinic and the William D. Coolidge Gold Medal from AAPM. Her research spans photon-counting CT, dual-energy CT, and translational imaging solutions for vascular and abdominal diseases. Dr. McCollough’s academic contributions include over 600 peer-reviewed publications and leadership in grant-funded projects such as the National Institute of Biomedical Imaging and Bioengineering initiatives. Education: PhD in Medical Physics from the University of Wisconsin-Madison, MS in Medical Physics from the University of Wisconsin-Madison, BS in Physics from Hope College. Research Highlights: Her lab develops tools for radiation dose estimation, non-invasive material characterization via CT, and optimizing CT parameters using human and model observers. Recent work includes improving kidney stone analysis, bone mineral density measurements using photon-counting CT, and reducing radiation exposure in pediatric imaging. Grants & Funding: Principal investigator on multiple NIH grants, including projects on coronary atherosclerosis characterization, urinary stone composition analysis, and photon-counting CT for vascular disease detection. Awards: Over 100 awards, including the Distinguished Mayo Clinic Investigator Award (2020), Honorary Doctorate from Linkoping University (2020), and AAPM’s highest honor, the William D. Coolidge Gold Medal (2024). Labs & Teams: Directs the CT Clinical Innovation Center and the X-Ray Imaging Research Core at Mayo Clinic, collaborating with multidisciplinary teams across radiology, biomedical engineering, and physics.
Antonio Maria Gonzalez Colas is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture within the Faculty of Computer Science of Barcelona (FIB). He leads the ARCO research group focused on Microarchitecture and Compilers and is actively engaged in high-impact research in computer architecture, GPUs, and energy-efficient computing. His collaborations extend to the Barcelona Supercomputing Center and various national and European research initiatives. Research Interests: His primary research areas include computer architecture, microarchitecture, compilers, GPUs, and processor design. He focuses on energy-efficient computing, deep neural network (DNN) accelerators, GPU simulation and optimization, memory systems, and architectural support for machine learning and autonomous systems. His work often integrates compiler techniques with hardware design for performance and efficiency. Scientific Production Trends: His recent publications demonstrate a strong focus on energy-efficient hardware for AI workloads, particularly DNN and speech recognition acceleration, GPU architectural innovations, memory optimization, and real-time rendering. He frequently publishes in top-tier venues such as ISCA, MICRO, HPCA, and IEEE/ACM journals. ICREA Academia Award 2024 HiPEAC 2024 Paper Award ACM Senior Member (2020) Advising and Grants: He has advised numerous PhD students whose theses cover topics like energy-efficient architectures for autonomous driving, speech recognition, and neural networks. He leads competitive R&D projects, including an ERC Advanced Grant and projects funded by the Spanish National Program and the ICREA Academia program, focusing on domain-specific architectures and cognitive computing units. Labs and Teams: He is the principal investigator of the ARCO (Microarchitecture and Compilers) research group at UPC, a leading team in computer architecture research in Spain. The group is part of a larger collaborative network within UPC and with international partners.
Hamed Nemati is an Assistant Professor at the Division of Network and Systems Engineering under the School of Electrical Engineering and Computer Science at KTH Royal Institute of Technology in Stockholm, Sweden. He was previously a Visiting Assistant Professor at Stanford University and a Research Group Leader at the Helmholtz Center for Information Security (CISPA) , where he also worked as a PostDoc and Research Fellow. Education : PhD in Computer Science from KTH Royal Institute of Technology Research Interests : Security of systems software, formal methods and program logics, interactive theorem proving, machine code analysis, applied machine learning Current Projects : Systematic verification of multi-language security protocols, hardware-software co-design for Spectre mitigation, capability-based access control models Scientific Awards : WASP (Wallenberg AI, Autonomous Systems and Software Program) faculty member Teaching Activities : Formal Methods in Security (Fall 2020-2023) at CISPA/Saarland University Digital Forensics and Incident Response (EP2780) (Fall 2024) at KTH
Changhee Jung is the Samuel D. Conte Associate Professor in the Department of Computer Science at Purdue University. His research focuses on compilers and computer architecture with an emphasis on performance, reliability, and security. His educational background includes a Ph.D. from Georgia Tech (2013) under the supervision of Prof. Santosh Pande. Professor Jung's research spans compilers and computer architecture with a focus on performance, reliability, and security. He has developed program analysis and microarchitecture optimization techniques for soft error resilience, concurrency bug detection, and system security such as memory safety and Linux kernel permission check. Currently, he is working on energy-efficient intermittent computation and nonvolatile memory crash consistency. He often leverages compiler-architecture codesign and repurposes existing hardware features to develop cost-effective solutions for complex computing challenges. His recent publications demonstrate a clear trajectory toward intermittent computing systems, nonvolatile memory architectures, and security mechanisms for energy-constrained environments. His work shows innovative approaches to power failure recovery, capacitor vulnerability exploitation, and EMI attack defense in intermittent systems, with significant contributions to whole-system persistence, cache design, and prefetching techniques for low-power computing. His notable scientific achievements include: NSF CAREER Award (2018) Inducted into MICRO Hall of Fame (2021) Best Paper Honorable Mention in ISCA 2025 Memorable Paper Award Finalist in NVMW 2024 Dissertation Advisor of 2023 ACM SIGBED Paul Caspi Memorial Dissertation Award winner Jongouk Choi 2017 AMD Faculty Research Award Professor Jung has successfully advised numerous graduate students, many of whom have secured prominent positions at leading technology companies including Google, Intel, and Samsung Electronics. His lab, the CompArch (Compiler and Architecture) research group, was formed in 2013 at Virginia Tech and continues at Purdue, focusing on compiler-architecture cooperation to address cross-cutting concerns involving performance, reliability, and security. The lab has received significant research funding, including an NSF CAREER Award in 2018 and an AMD Faculty Research Award in 2017.
Professor Per Stenström is affiliated with the Department of Computer Science and Engineering at Chalmers University of Technology . His research focuses on computer architecture , memory systems optimization , and energy-efficient computing , with significant contributions to DNN accelerator design and cache management . Research Trends : His recent publications emphasize Memory compression techniques for energy efficiency Hardware-software co-design for DNN acceleration Security in microarchitectural optimizations Hybrid memory systems for near-memory computing These works span both theoretical and applied aspects of computer architecture, with a particular focus on data redundancy elimination , parallel processing , and quality-of-service constraints . His work has influenced the development of energy-aware resource management frameworks and resilient EU HPC systems , as evidenced by his long-standing contributions to the field since the early 2010s.
Mircea R. Stan is a Professor of Electrical and Computer Engineering at the University of Virginia, serving as Director of Computer Engineering and Virginia Microelectronics Consortium (VMEC) Professor. He leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). His research focuses on AI hardware, Processing in Memory, Low Power Design, Cyber-Physical Systems, and Spintronics. Education: Ph.D. (1996) and M.S. (1994) from UMass Amherst; Diploma (1984) from Politehnica University, Bucharest. Research interests include energy-efficient computing architectures, IoT systems, and emerging technologies like magnetic skyrmions and memristors. He has pioneered work on asynchronous stochastic computing, thermal-aware microarchitecture, and microfluidic cooling for 3D-ICs. Key awards include the 2024 A. Richard Newton Technical Impact Award, 2018 ISCA Influential Paper Award, and IEEE Fellow (2014). He has held editorial roles at IEEE TVLSI, IEEE TNano, and IEEE Design & Test. Notable contributions include the HPLP lab’s advancements in low-power logic computing, the VCRFID framework for Industry 4.0, and thermal-aware design tools like Hot-LEGO and Cool-3D.
Prof. Dr.-Ing. Rüdiger Kapitza serves as a Professor and Chair of Computer Science 4 (Systems Software) at Friedrich Alexander University Erlangen-Nuremberg (FAU). His extensive research portfolio spans trusted execution environments, Byzantine fault tolerance, blockchain technology, and secure systems. Kapitza actively contributes to the academic community through program committee roles for major conferences including OSDI, Middleware, EuroSys, and DSN. His research interests focus on creating secure, reliable systems through the integration of hardware security features with distributed systems. Kapitza investigates how trusted computing can enhance system security while maintaining performance, particularly for critical applications. His work bridges theoretical foundations with practical implementations across domains including cloud infrastructure, edge computing, and transportation systems. Analysis of his recent publications reveals consistent innovation in trusted execution environments, distributed consensus protocols, and secure virtualization. His research demonstrates a clear trajectory from early work on adaptive services to current focus on hardware-assisted security solutions. Key themes include making distributed systems more robust through trusted components, optimizing energy efficiency in heterogeneous systems, and developing practical security solutions for real-world applications. Prof. Kapitza's standing in the systems research community is evidenced by his service on program committees for top-tier conferences. His work has been published in prestigious venues including OSDI, EuroSys, Middleware, and DSN, reflecting significant impact in both academic and industrial contexts. He leads the Systems Software research group at FAU, mentoring students and collaborating with researchers worldwide. The group addresses fundamental challenges in systems security, reliability, and performance, with applications ranging from drone data recording to railway systems and secure cloud services. His team develops practical tools and frameworks that advance the state of the art in systems research.
Ramon Canal is a Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Barcelona School of Informatics and the Computer Architecture Department. He has served as Vice Dean of postgraduate studies and leads the VirtuOS (Virtualization and Operating Systems) research group. His academic background includes BSc, MSc, and PhD from UPC, with thesis supervision by Antonio González (UPC) and James E. Smith (University of Wisconsin-Madison). He completed sabbaticals at Harvard University (2006-2007) and University of Cyprus (2019-2020). Education: PhD, MSc, BSc in Computer Engineering (UPC) Research focus: Microarchitecture security, reliability across circuit/system levels, cloud optimization Recent publications address privacy in IoT, secure hardware accelerators, and safety-critical systems. His work contributes to the DRAC project (2019-2022), Red-RISCV network, and Horizon's Vitamin-V project. Awards include HiPEAC Paper Awards, IEEE Senior Member status, Fulbright recognition, and multiple education excellence accolades. Scientific Honors HiPEAC Paper Award (ISCA-44, 2017) IEEE Senior Member (2016) Best Paper Nominee (ICCD-32, 2014) UPC Outstanding PhD Award supervision (2011) He advises current MSc students and has mentored multiple PhD graduates. Professional activities span academic leadership, research collaborations with Barcelona Supercomputing Center (BSC), and technical contributions to reliability analysis frameworks like RECIPE and FRACTAL.
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