Martin Radetzki is a full Professor at the Institute for Computer Architecture and Parallel Systems (University of Stuttgart) , specializing in Embedded Systems . His work focuses on network-on-chip (NoC) design, fault tolerance, memory optimization, and simulation frameworks. Key research areas: NoC synthesis, deadlock-free routing, performability analysis, and power-efficient memory subsystems Recent publications emphasize integer linear programming frameworks for co-designing floorplanning and routing, chiplet-based systems , and machine learning-enabled performance evaluation His methodologies address cross-layer challenges in NoC design, combining formal optimization with practical implementation for heterogeneous processing elements. Collaborative projects include fault resilience analysis, parallel simulation techniques, and memory allocation strategies for SoCs. Dr. Radetzki supervises research with students like Shuang Liu and Manuel Strobel , contributing to IEEE Transactions on Computers , ACM TECS , and conferences such as DATE and MCSoC . Current work explores optimal routing topologies for emerging chip architectures.
Ganesh Subbarayan is the James G. Dwyer Professor of Mechanical Engineering at Purdue University, affiliated with the School of Mechanical Engineering. His roles include leading the Institute for Advanced System Integration and Packaging (ASIP) and the Center for Heterogeneous Integration Research in Packaging (CHIRP). He holds a B.Tech. from IIT, and M.S. and Ph.D. from Cornell University. His research focuses on computational and experimental solid mechanics, particularly in fatigue, fracture, and multi-physics phase evolution. Key areas include advanced electronics packaging, solder joint reliability, and thermomechanical behavior. Techniques employed include Finite Element Analysis (FEA), Isogeometric Analysis (IGA), and machine learning for multiphysics modeling. Recent work emphasizes heterogeneous integration challenges, real-time thermal simulations, and non-destructive material characterization. His publications span 20+ years, addressing topics like solder microstructure evolution, electromigration, and thermal management in 3D packaging. Prof. Subbarayan has contributed to over 100 peer-reviewed articles and holds leadership in interdisciplinary research initiatives at Purdue. His lab, HiDAC, develops novel methods for analyzing complex material systems.
Christophe Bobda is a Citi Endowed Professor in Advanced Technologies and Associate Chair for Academics at the University of Florida's Department of Electrical & Computer Engineering within the Herbert Wertheim College of Engineering. His research focuses on FPGA-based systems, cybersecurity, embedded systems, and resilient architectures. He holds a Ph.D. from the University of Paderborn, Germany, and degrees from Universities in Germany and Cameroon. Research interests include System-on-Chip design, reconfigurable computing, and robotics. Notable contributions span secure cloud FPGA deployment, multi-tenant hardware security, and near-sensor processing architectures. He received the HWCOE International Educator of the Year award in 2024. Recent work emphasizes FPGA security in cloud environments, with projects like CIVIC-FPGA and ISO-TENANT addressing isolation and attack mitigation. His lab explores embedded imaging and robotics applications, leveraging low-power and high-performance FPGA solutions. NSF grants support his research in FPGA acceleration and datacenter infrastructure. Publications highlight advancements in event-based vision systems, 3D semantic modeling, and hardware trojan detection. Ongoing projects include chiplet interfaces for on-device AI and galvanic isolation for physical attack prevention. His work bridges theoretical cybersecurity with practical FPGA implementations for resilient systems.
Gianluca Mittone is a postdoctoral researcher at the University of Turin's Computer Science Department, affiliated with the Parallel Computing group. His work bridges High-Performance Computing (HPC) and Artificial Intelligence (AI), focusing on Federated Learning (FL) as a privacy-preserving, scalable solution for AI applications. Co-Principal Investigator for FL-as-a-Service platform in TIM Edge & Cloud Continuum IPCEI project Recipient of HPC-Europa3 and EuroPar Foundation awards Research interests center on FL deployment in HPC/cloud environments , including RISC-V hardware exploration for decentralized AI, cross-facility FL workflows, and HPC benchmarking. Publications demonstrate expertise in privacy-preserving AI , edge inference , and medical applications like cardiovascular diagnostics through machine learning. Article analysis reveals integration of HPC systems with emerging AI architectures (including Large Language Models), with subfields spanning confidential FL , drug-target interaction , survival analysis , and RISC-V AI frameworks . Awards highlight recognition in both HPC and FL domains, while collaborations with Telecom Italia and participation in TEXTAROSSA project underscore industry-academia impact. HPC-Europa3 scholarship EuroPar foundation studentship Best PhD Symposium Award (EuroPar 2023) PRAISE Score endorsed by European Society of Cardiology (2023 guidelines)
Bo Zhao is an Assistant Professor in the Department of Computer Science at Aalto University, leading the Aalto Data-Intensive System group (ADIS). His research focuses on building efficient data-intensive systems across multiple layers, from scalable machine learning systems to distributed data management systems. Research Focus: Scalable machine learning systems Distributed data processing Hardware-software co-design Quantum computing systems High-performance computing Current Projects: AthenaRL (scalable RL systems), LARA (quantum ML algorithms), FlexMoE (efficient mixture-of-experts systems). His group develops systems enabling ML deployment across hardware from quantum computers to mobile devices. Education & Career: PhD from Humboldt-Universität zu Berlin. Previously at Queen Mary University of London, Imperial College London, and Amazon Web Services. Research published in SOSP, VLDB, USENIX ATC.
Miltiadis Moralis-Pegios is a Lecturer at the Department of Informatics, School of Informatics, Aristotle University of Thessaloniki (AUTH). He has been actively involved in academic teaching and research projects since 2002. Current Courses : Information Theory and Coding (Spring 2024–25) Research Interests : Focus on silicon photonics, neuromorphic computing, and optical networking for high-speed data centers. Applications include graphene-based secure IoT, environmental pollution detection via hyperspectral sensors, and plasmonic circuits for AI hardware. Notable Research : Participation in projects like Heterogeneously integrated photonic chiplets for AI engines , Smart environmental sensing systems , and Graphene optical platforms (2024–2027). Earlier work includes optical transceivers for data centers and flood risk management systems. Collaborations : Extensive involvement in EU-funded initiatives (EDAR, IN LIFE, HARC) and national projects (e.g., VERITAS , Archimedes ).
Michael Meidinger is a doctoral student and scientific assistant at the Chair of Integrated Systems within the TUM School of Computation, Information and Technology at the Technical University of Munich. His research focuses on chiplet architectures (interconnect design and smart functionalities) and reinforcement learning for runtime optimization of MPSoCs and autonomous driving systems. Education: B.Sc. and M.Sc. in Electrical Engineering and Information Technology (2018–2023) from TUM He contributes to projects like the BCDC chiplet-based system and the Duckietown Lab , where he develops tools for autonomous driving research, such as DuckieVisualizer. He supervises student projects in areas including interconnect protocol enhancements, robotics, and real-time object recognition.
Gokul Ravi is a Professor in the Department of Computer Science and Engineering at the University of Michigan. His research focuses on quantum computing, quantum algorithms, compiler optimization for quantum systems, and computer architecture. He leads a research group emphasizing impactful research in quantum domains, with weekly one-on-one and group meetings fostering collaboration and community. Students benefit from lab lunches where they discuss projects, papers, and potential collaborations. He prioritizes clear communication, with expectations including 5-6 years of PhD tenure and 3+ top-tier publications. Research interests span variational quantum algorithms, error mitigation, quantum cloud computing, and hardware-software co-design. His work addresses challenges in fault-tolerant quantum computing, compiler passes for NISQ applications, and quantum-centric supercomputing for materials science. Recent publications highlight innovations in quantum algorithm design, error correction, and hybrid systems. Students receive weekly progress updates and yearly feedback. He supports internships (up to 2) aligned with research and facilitates conference attendance via travel grants. Vacation planning is flexible but avoids deadlines. His mentoring style adapts to individual student needs, balancing independence with mentorship, particularly in early PhD stages.
Maciej Besta is a leading researcher at ETH Zurich's Institute for Computing Platforms, where he heads research initiatives at the Scalable Parallel Computing Lab (SPCL) and contributes to the ETH Future Computing Laboratory (EFCL). Working under the mentorship of Professor Torsten Hoefler, he has established himself as a prominent figure in high-performance computing, graph processing, and large language models. Position: Researcher at Institute for Computing Platforms, ETH Zurich Research Leadership: Head of Sparse Graph Computations and Large Language Models Research at SPCL Collaboration: Leads project management for SPCL's contributions to ETH Future Computing Laboratory Besta's research spans multiple abstraction levels, from hardware and network topologies to middleware, algorithms, and programming models. His primary focus areas include graph-enhanced language models, graph neural networks, graph databases, and sparse models, with applications across various computational settings. He approaches these problems through rigorous performance modeling and formal reasoning, emphasizing both scalability and practical implementation. His recent publications reveal a clear trend toward integrating graph structures with language models and AI systems. Besta has pioneered work on graph databases, knowledge graphs of thoughts, and higher-order graph neural networks, while maintaining his strong foundation in high-performance computing and network topology design. His research bridges traditional HPC with cutting-edge AI, creating novel approaches for efficient large-scale computation. IEEE TCSC Award for Excellence in Scalable Computing (Early Career, 2023) Multiple Best Paper Awards at Supercomputing conferences (2022, 2023) ACM SIGHPC Doctoral Dissertation Award (2022) ETH Medal for outstanding doctoral thesis (2021) Fellow of The Explorers Club (2022) Besta actively mentors ETH Zurich students through semester projects, Bachelor's, and Master's theses, focusing on graph processing and related computer science challenges. His mentorship extends beyond technical guidance, incorporating lessons from his extensive polar and mountaineering expeditions that emphasize mental resilience, efficient risk management, and leadership. He has supervised numerous student projects that have resulted in high-impact publications at top-tier conferences. As a core member of the Scalable Parallel Computing Lab, Besta collaborates with researchers across ETH Zurich and international institutions. His unique approach integrates insights from extreme environment expeditions into research methodology, creating a distinctive framework for tackling complex computational problems. The lab's work under his leadership spans theoretical modeling, practical implementation, and real-world deployment of high-performance systems.
Selçuk Köse is a Full Professor in the Department of Electrical and Computer Engineering at the University of Rochester. Previously, he held positions at the University of South Florida as an Assistant Professor (2012-2018) and Associate Professor (2018-2019). He earned his B.Sc. from Bilkent University (2006), M.S. and Ph.D. from the University of Rochester (2008 and 2012, respectively). His research focuses on hardware security (side-channel attacks, fault injection, PUFs), on-chip power delivery, cryogenic electronics, graphene nanoribbon transistors, and nature-inspired computing (e.g., Ising machines). He has received prestigious awards including the NSF CAREER Award (2014) and Cisco Research Awards (2015–2017). His recent work emphasizes security in quantum computing interfaces, power delivery networks, and covert channel mitigation. Research funding comes from NSF, DARPA, DoE, and industry partners. He serves as an associate editor for IEEE and Springer journals.
Rafael Medina Morillas is a researcher at the Embedded Systems Laboratory (ESL) at Ecole Polytechnique Fédérale de Lausanne (EPFL), where he focuses on computer architecture and hardware acceleration for edge AI systems. His research addresses the memory wall problem through innovative architectural designs that improve energy efficiency and performance in data-intensive applications. His primary research interests include: Compute-near-Memory architectures Hardware acceleration for machine learning Edge AI systems Chiplet architectures and interconnects Wireless communication for computing systems Medina Morillas' publication record demonstrates significant advancements in memory systems and hardware acceleration. His work on SideDRAM shows up to 83% EDAP reduction compared to state-of-the-art designs, while his research on wireless communication achieves up to 2.64x speedup for deep neural networks. His recent publications focus on structured pruning techniques for transformers, co-design frameworks for edge AI, and thermal management solutions for heterogeneous systems. His research is supported by collaborations with IMEC, Université de Bordeaux, and HEIG-VD, as well as funding from EC H2020 projects and the ACCESS-AI Chip Center. These partnerships enable comprehensive exploration of architectural innovations across different technology domains. As evidenced by his doctoral thesis 'System-aware Architectural Co-design to Tackle the Memory Wall,' Medina Morillas takes a cross-layer approach to system design, integrating hardware and software optimizations to address fundamental bottlenecks in modern computing systems. His work demonstrates how system-aware architectural design can achieve improvements in runtime, energy consumption, and thermal behavior for data-intensive applications.
