Martin Radetzki

Martin Radetzki is a full Professor at the Institute for Computer Architecture and Parallel Systems (University of Stuttgart), specializing in Embedded Systems. His work focuses on network-on-chip (NoC) design, fault tolerance, memory optimization, and simulation frameworks.

• Key research areas: NoC synthesis, deadlock-free routing, performability analysis, and power-efficient memory subsystems
• Recent publications emphasize integer linear programming frameworks for co-designing floorplanning and routing, chiplet-based systems, and machine learning-enabled performance evaluation

His methodologies address cross-layer challenges in NoC design, combining formal optimization with practical implementation for heterogeneous processing elements. Collaborative projects include fault resilience analysis, parallel simulation techniques, and memory allocation strategies for SoCs.

Dr. Radetzki supervises research with students like Shuang Liu and Manuel Strobel, contributing to IEEE Transactions on Computers, ACM TECS, and conferences such as DATE and MCSoC. Current work explores optimal routing topologies for emerging chip architectures.