Klajd Zyla

Klajd Zyla is a PhD student and scientific assistant at the Chair of Integrated Systems, TUM School of Computation, Information and Technology, Technical University of Munich. His research focuses on architectures for flexible data packet processing in high-performance network cards, including NoC optimization, priority-aware scheduling, and RDMA acceleration.

• PhD Student at LIS (Chair of Integrated Systems), Technical University of Munich (since Jan 2022)
• Teaching: SystemC Laboratory (since SS 2022)

His research investigates on-chip interconnects, packet scheduling with multiple priorities, and acceleration of transport protocols like RDMA for FPGA-based SmartNICs. Publications demonstrate expertise in crossbar architectures, deadlock avoidance, and resource management for MPSoCs.

Supervised students include:

• Nour Abouelkheir (2D Mesh NoC design)
• Aleksa Stojkovic (HiPerNoC enhancement)
• Antra Pramanik (Packet-processing FPGA implementation)
• Arathi Anitha (Deadlock-avoidance algorithms)
• Johannes Ecker (Hardware schedulers comparison)