جست‌وجوی استاد و پژوهشگر

Chengmo Yangمشاهده پروفایل

استاد

• Embedded Systems
• Design Automation
• Computer Architecture
• +۶ مورد دیگر

Dr. Chengmo Yang is a Professor in the Department of Electrical and Computer Engineering at the University of Delaware, with a joint appointment. She received her PhD and MSc in Computer Science from the University of California, San Diego, and a BSc in Microelectronics from Peking University, China. PhD, University of California, San Diego MSc, University of California, San Diego BSc, Peking University, China Her research focuses on enhancing security, reliability, non-volatility, and energy efficiency in embedded systems, cyber-physical systems (CPS), and Internet-of-Things (IoT). She leads the Computer Architecture, Reliability, and Security (CARES) group and has authored over 70 peer-reviewed publications. Recent publications emphasize neural network accelerators, non-volatile memory (NVM) optimization, and security frameworks for embedded systems. Her work explores fault tolerance, wear leveling, and side-channel attack mitigation in NVM-based FPGAs, STT-RAM, and SSDs. National Science Foundation Career Award (2013) University of Delaware Mid-Career Faculty Excellence in Scholarship Award (2020) Best paper award at ICESS (2019) Three best paper nominations at DAC, DATE, and GLSVLSI (2019) Dr. Yang serves as Associate Editor for IEEE TCAD and ACM TODAES. She is the Diversity & Inclusion Representative for IEEE CEDA and has organized numerous conferences including Technical Program Chair for CODES-ISSS 2022. Her lab has hosted current and former students like Fanruo Meng (PhD candidate), Fateme Hosseini (Qualcomm), and Patrick Cronin (Intel), focusing on graduate-level research in hardware security and reliability.

Luca Beniniمشاهده پروفایل

استاد

• Computer Engineering
• Embedded Systems
• VLSI Design
• +۲ مورد دیگر

Luca Benini is a Full Professor at the Department of Information Technology and Electrical Engineering at ETH Zurich. He works at the Institute for Integrated Systems, located at Gloriastrasse 35, 8092 Zurich, Switzerland. His contact number is +41 44 632 66 64. Research Interests: Focus on VLSI design and FPGA-based systems development. Teaching: Offers the course VLSI 1: HDL Based Design for FPGAs in the Fall semester 2025. Contact: lbenini@iis.ee.ethz.ch

Tushar Krishnaمشاهده پروفایل

دانشیار

• Computer Architecture
• Interconnection Networks
• Networks-on-Chip
• +۴ مورد دیگر

Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology, with a courtesy appointment in the School of Computer Science. He earned his PhD in Electrical Engineering and Computer Science from MIT in 2014, an MSE in Electrical Engineering from Princeton University in 2009, and a B.Tech in Electrical Engineering from IIT Delhi in 2007. His research spans computer architecture, interconnection networks, networks-on-chip (NoC), and AI/ML accelerator systems, with a focus on optimizing data movement in modern computing platforms. His work is funded by NSF, DARPA, IARPA, SRC, Department of Energy, Intel, Google, Meta, Qualcomm, and TSMC. His papers have been cited over 17,000 times, with three receiving IEEE Micro's Top Picks recognition, one earning an honorable mention, and four winning best paper awards. Dr. Krishna leads the Synergy Lab at Georgia Tech and has developed several influential tools including ASTRA-sim for distributed AI/ML training, MAESTRO and SCALE-sim for accelerator design space exploration, and Garnet2.0 for NoC simulation. His recent work focuses on large language model acceleration, distributed training systems, and neuro-symbolic AI architectures. He has received numerous teaching and research awards including induction into the HPCA Hall of Fame (2022), the Class of 1940 Teaching Effectiveness Award (2018), and the Roger P. Webb Outstanding Mid-career Faculty Award (2024). HPCA Hall of Fame Inductee (2022) Roger P. Webb Outstanding Mid-career Faculty Award (2024) Richard M. Bass/Eta Kappa Nu Outstanding Junior Teacher Award (2023) Roger P. Webb Outstanding Junior Faculty Award (2021) Class of 1940 Course Survey Teaching Effectiveness Award (2018) Dr. Krishna currently serves as Associate Director for the Center for Research into Novel Computing Hierarchies (CRNCH) and co-chair of the Chakra Execution Traces and Benchmarks Working Group. He has held the ON Semiconductor (Endowed) Junior Professorship at Georgia Tech (2019-2021) and has been a visiting professor at MIT EECS, Harvard University CS, and a researcher at Intel's VSSAD group.

Benjamin Carrison-Schaferمشاهده پروفایل

دانشیار

• Reconfigurable Computing
• FPGAs
• Electronic Design Automation
• +۷ مورد دیگر

Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.

Bahar Asgariمشاهده پروفایل

استادیار

• Computer Architecture
• Domain-Specific Architecture Design
• Near Memory Processing
• +۳ مورد دیگر

Bahar Asgari is an Assistant Professor in the Department of Computer Science at the University of Maryland, College Park. She holds appointments in CS, UMIACS, and ECE, and directs the Computer Architecture and Systems Lab (CASL). Her research focuses on domain-specific architecture design, near memory processing, and reconfigurable computing. Before joining UMD, she worked at Google, contributing to system optimization and memory utilization strategies. Education: Ph.D., Georgia Institute of Technology, 2021. Research Interests: Developing energy-efficient architectures for sparse problems, scientific computing acceleration, FPGA optimizations, and reconfigurable hardware systems. Her work addresses challenges in memory efficiency, parallelization, and hardware-software co-design across domains like machine learning and IoT. Key Awards: 2024 UMD Excellence in Teaching Award 2023 DOE Early Career Award Advising & Grants: Supervises 9 graduate students and leads projects sponsored by NSF, DOE, and industry partnerships. Her lab explores systolic arrays, near-data processing, and fault-tolerant computing. Labs/Teams: Directs CASL, which builds next-generation computing systems through hardware innovation and algorithm-architecture co-design.

Giovanni De Micheliمشاهده پروفایل

استاد

• Integrated Circuit Design
• Hardware Synthesis
• Logic Optimization
• +۵ مورد دیگر

Giovanni De Micheli is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL), holding appointments in both the School of Computer and Communication Sciences (IC) and the School of Engineering (STI). He is affiliated with the Integrated Systems Laboratory (LSI) and serves as Scientific Director of EcoCloud. His primary office is located in INF 341 building at EPFL's Lausanne campus where he conducts research and teaching activities. Professor De Micheli's research spans multiple domains in electronic design automation and integrated circuit design. His primary interests include: Integrated Circuit Design and Hardware Synthesis Logic Optimization and Boolean Methods Nanoelectronics and 2D Electronics Quantum Computing and Emerging Technologies Low-Power Electronics and Energy-Efficient Systems Electronic Design Automation for Novel Computing Paradigms His recent publications demonstrate a strong focus on advancing logic synthesis techniques for both conventional and emerging technologies. Professor De Micheli's work bridges theoretical foundations with practical applications, particularly in adapting traditional EDA methods to novel computing paradigms like quantum computing and superconducting electronics. His research group has made significant contributions to the development of efficient algorithms for circuit optimization across multiple technology domains, with particular emphasis on area, power, and delay optimization while maintaining functional correctness. Professor De Micheli has supervised numerous doctoral students throughout his career at EPFL, mentoring over 40 PhD candidates whose research spans various aspects of electronic design automation, circuit design, and emerging technologies. His students have gone on to make significant contributions in both academia and industry. As Scientific Director of EcoCloud, Professor De Micheli leads research initiatives focused on energy-efficient computing systems and sustainable cloud infrastructure. His laboratory, the Integrated Systems Laboratory, serves as a hub for interdisciplinary research connecting computer science, electrical engineering, and materials science, with particular focus on next-generation computing technologies.

Shweta Shindeمشاهده پروفایل

استادیار

• Trusted Computing
• System Security
• Program Analysis
• +۴ مورد دیگر

Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.

Michael O'Boyleمشاهده پروفایل

استاد

• Heterogeneous Code discovery and Optimisation
• Neural Machine Translation and Neural Synthesis
• Deep Neural Network system stack
• +۷ مورد دیگر

Michael O'Boyle is a Professor at the University of Edinburgh's School of Informatics, where he serves as Director of the ARM Research Centre of Excellence and the EPSRC Centre for Doctoral Training in Pervasive Parallelism. Holding an EPSRC Established Career Research Fellowship, he leads pioneering work in compiler technology for heterogeneous architectures, bridging theoretical advances with practical high-performance computing applications. Professor O'Boyle's research spans multiple cutting-edge areas including heterogeneous code discovery and optimization, neural machine translation for program synthesis, deep neural network system stack optimization, software-defined hardware, and compiler/architecture co-design. His approach integrates constraint analysis, program synthesis, and machine learning to address complex challenges in high-performance computing across diverse hardware platforms. His recent publications reveal a strong trend toward integrating machine learning with traditional compiler techniques, particularly in neural program synthesis, tensor optimization, and architecture-aware compilation. This work represents a paradigm shift in compiler design, moving from rule-based systems to learning-based approaches that can automatically adapt to diverse hardware targets. IEEE/ACM CGO 2025 Distinguished Paper Award for 'Tensorize: Fast Synthesis of Tensor Programs from Legacy Code' IEEE/ACM CGO 2024 Test of Time Award ACM GPCE 2023 Best Paper Award for 'C2TACO: Lifting Tensor Code to TACOM' ACM ASPLOS 2021 Distinguished Paper Award IEEE HPCA 2021 Best Paper Award for 'Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads' Professor O'Boyle has successfully mentored numerous PhD students who have secured prominent positions in academia (including at Cambridge, Edinburgh, Leeds, and McGill) and industry (including Meta, NVIDIA, Qualcomm, Huawei, and Microsoft). His research is supported by significant funding from EPSRC, ARM, and European projects including Bonseyes and Transmuter, demonstrating strong international recognition and industry impact. He leads the influential Compiler and Architecture Design (CArD) Group at the University of Edinburgh and is a founder of the HiPEAC Network of Excellence, which has grown into a major European initiative connecting researchers and practitioners in high-performance and embedded computing.

Gustavo Alonsoمشاهده پروفایل

استاد

• Databases
• Distributed Systems
• Cloud Computing Architecture
• +۴ مورد دیگر

Gustavo Alonso is Full Professor at the Department of Computer Science (D-INFK) of ETH Zurich and Head of the Institute for Computing Platforms . He has been at ETH since 1995, first as a post-doc, then as Assistant Professor from April 1998, and promoted to Full Professor in October 2001. Within the Systems Group he leads the Information and Communication Systems Research Group . Education: 1989 – Telecommunications Engineering (undergraduate), Madrid Technical University (UPM-ETSIT), Spain 1992 – M.S. Computer Science, University of California, Santa Barbara (UCSB) 1994 – Ph.D. Computer Science, University of California, Santa Barbara (UCSB) Research Interests: His work spans databases, distributed systems, cloud-computing architecture, FPGAs, hardware acceleration for data science, parallel and reconfigurable computing . The group investigates how modern heterogeneous hardware—from GPUs to SmartNICs—can be integrated into data-processing systems to achieve orders-of-magnitude performance gains, energy savings, and new functionality such as in-network computation and serverless acceleration. Scientific Awards & Honors: Fellow of the ACM (Association for Computing Machinery) Fellow of the IEEE (Institute of Electrical and Electronics Engineers) Distinguished Alumnus, Department of Computer Science, UC Santa Barbara Four Test-of-Time / Most Influential Paper Awards across databases, programming languages, cloud computing, and software engineering Labs & Projects: He directs the Information and Communication Systems Research Group within the Systems Group ( systems.ethz.ch ). The lab develops open-source platforms such as Coyote v2 for FPGA abstractions, Shuhai for HBM benchmarking, and MicroRec for micro-second recommendation serving, while collaborating with industry on SmartNICs, serverless analytics, and cloud-scale data analytics.

Timothy Roscoeمشاهده پروفایل

استاد

• Operating Systems
• Networking
• Distributed Systems
• +۳ مورد دیگر

Prof. Dr. Timothy Roscoe is a Full Professor in the Department of Computer Science at ETH Zurich. His research focuses on operating systems, networking, and distributed systems. He was inducted as an ACM Fellow in 2014 for contributions to these fields. Previously, he worked at Intel Research Berkeley, UC Berkeley (Adjunct Professor), and Sprint Labs. His work includes foundational contributions to systems like PlanetLab, P2 Declarative Networking, and the Nemesis OS. Roscoe holds a PhD from the University of Cambridge and has led projects in cloud computing, wide-area network measurement, and secure systems design. His current research emphasizes hardware-software co-design, formal verification of systems, and scalable memory architectures. Education: PhD in Computer Science, University of Cambridge (1995) Key Roles: Principal Researcher at Intel Berkeley Lab, Visiting Researcher at National ICT Australia Research Highlights: Contributions to distributed systems (PlanetLab), declarative networking (P2), and secure microkernels (seL4 integration). Current projects address challenges in disaggregated memory systems, coherent interconnects, and trustworthy embedded systems. Awards: ACM Fellow (2014), numerous grants and industry collaborations. Labs/Teams: Systems Group at ETH Zurich, focusing on OS design, hardware architectures, and formal methods.

James C. Hoeمشاهده پروفایل

استاد

• Computer Architecture
• Reconfigurable Computing
• High-Level Hardware Design and Synthesis
• +۴ مورد دیگر

James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University (College of Engineering). He is on sabbatical at MangoBoost and directs research in computer architecture, reconfigurable computing, and high-level hardware design. Education Ph.D., Electrical Engineering and Computer Science, MIT (2000) M.S., Electrical Engineering and Computer Science, MIT (1994) B.S., Electrical Engineering and Computer Science, UC Berkeley (1992) Research Interests Professor Hoe’s work spans computer architecture , reconfigurable computing , FPGA architectures , and high-level hardware synthesis . His group created the CoRAM abstraction for virtualized FPGA computing and leads efforts in power-efficient accelerators, in-network computing, and security-oriented FPGA systems. Scientific Awards IEEE Fellow (2013) Intel Outstanding Researcher Award (2021) Research Funding & Projects Intel / VMware Crossroads 3D-FPGA Academic Research Center – co-leading exploration of FPGA roles in future datacenters. DARPA BRASS program ($2.7 M, 4 years) – ensuring long-lived software systems remain robust to resource changes. Pigasus open-source IDS – world’s fastest FPGA-accelerated intrusion-detection system (100 Gb/s on one server). Labs & Teams He heads activities within the Computer Architecture Lab at Carnegie Mellon (CALCM) , supervising graduate researchers on CoRAM++, SPIRAL autotuning, and FPGA overlays for stream processing.

Jan Madsenمشاهده پروفایل

استاد

• Embedded Systems
• Cyber-Physical Systems
• Microfluidic Biochips
• +۵ مورد دیگر

Jan Madsen is a Professor at DTU Compute, Technical University of Denmark, and Head of the Embedded Systems Engineering section. His research focuses on system-level modeling and design of embedded computing systems, particularly cyber-physical systems, microfluidic biochips, and synthetic biology applications. Develops design automation tools and methodologies for embedded systems Supervises numerous PhD students and leads major research projects Research Interests Key areas include: Embedded systems-on-a-chip Cyber-Physical Systems (Internet-of-Things) Microfluidic Lab-on-Chip devices Synthetic biology with molecular computing Design, modeling, and optimization of complex systems Scientific Awards DATE Fellow (2019) IEEE CEDA Outstanding Recognition (2019) DTU Scientific Advise Award (2013) Best Paper Awards at MECO (2013) and CASES (2009) Jorck’s Foundation Research Award (1995) Publications His 14+ journal papers and 115+ conference papers demonstrate expertise in: SystemC-based modeling frameworks Energy-aware sensor networks Self-healing eDNA architectures Microfluidic biochip synthesis RTOS modeling and MPSoC exploration

Hayden Kwok Hay SOمشاهده پروفایل

دانشیار

• Reconfigurable Computing
• FPGA-Based Systems
• Computer Architecture
• +۷ مورد دیگر

Prof. Hayden Kwok Hay SO is an Associate Professor at the University of Hong Kong (HKU), affiliated with the Department of Electrical and Electronic Engineering. He currently serves as Acting Director of the School of Innovation and previously co-directed the Computer Engineering Program. His research focuses on reconfigurable computing systems, FPGA-based architectures, and their applications in AIoT, medical imaging, and high-performance computing. He holds a B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley (1998–2007). Prof. So has been recognized with awards such as the IEEE-HKN Teaching Award (2021), Croucher Innovation Award (2013), and multiple teaching excellence awards. He leads the Computer Architecture & System Research Lab (CASR) and co-founded the Joint Lab on Future Cities (JLFC). His work spans FPGA overlay architectures, graph processing systems, and hardware-software co-design for efficient computing. Key research contributions include advancements in FPGA-based reconfigurable systems, sparse dataflow architectures, and medical imaging accelerators. He has secured grants for projects like 'Advanced machine vision guided aquatic surface vehicles' and 'Efficient and Productive Parallel Data Processing in Hybrid FPGA-CPU Clusters.' Prof. So has advised numerous students and researchers, contributing to over 150 peer-reviewed publications. His current projects explore AI hardware acceleration, neuromorphic computing, and FPGA-driven solutions for big data challenges.

• Reconfigurable Computing
• FPGA Architectures
• Computer Security
• +۶ مورد دیگر

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, affiliated with Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS). He chairs the Computer Engineering (CMPE) program and directs the CyberSavvy Security Center. His research focuses on reconfigurable computing, FPGA architectures, computer security, and energy-efficient hardware design. He holds a Ph.D. and M.S. from MIT and a B.S. from MIT's Lincoln School. Research interests include reconfigurable computing, FPGA interconnect, hardware security, and fault-tolerant systems. Notable achievements include the SEVER & PROTECT DARPA award and IEEE/ACM Fellowships. Recent work addresses fast FPGA compilation (HiPR, PLD), security through compartmentalization (μSCOPE, SCALPEL), and partial reconfiguration techniques. Teaching includes courses on hardware security, system-on-chip architecture, and digital audio basics. Over 200 publications span FPGA design, network-on-chip optimization, and molecular-scale computing. His labs (Implementation of Computation Group) explore physical implementation of computations through hardware-software co-design.

Scott Hauckمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Architecture
• Quantum Computing Control
• +۵ مورد دیگر

Affiliation & Education Scott Hauck is a Professor at the University of Washington's Department of Electrical & Computer Engineering and an Adjunct Professor in Computer Science & Engineering. He leads the Adaptive Computing Machines and Emulators (ACME) Lab . He earned his BS in EECS from UC Berkeley (1990), and MS/PhD in CSE from the University of Washington (1992/1995). Research Focus Dr. Hauck specializes in FPGA-based reconfigurable computing with applications in: Quantum Computing: FPGA controllers for trapped-ion quantum systems enabling precise laser control and quantum state readout. Medical Imaging: Portable radiation sensors for personalized cancer therapy and PET scanner enhancements. High-Energy Physics: FPGA readout systems for ATLAS pixel detectors at CERN's Large Hadron Collider. AI Acceleration: Real-time machine learning inference for scientific applications via projects like hls4ml. His work bridges hardware innovation with computational physics, emphasizing real-time processing and low-latency systems. Publication Trends Recent research focuses on FPGA-accelerated machine learning for particle physics (e.g., transformer networks for LHC trigger systems) and quantum computing instrumentation. Earlier work established foundations in reconfigurable computing architectures and medical imaging electronics. Awards & Recognition Distinguished Teaching Award, University of Washington (2010) Advising & Funding Leads the ACME Lab with extensive funding from NSF, DARPA, NIH, DOE, and industry partners including Intel, Xilinx, and Microsoft. Mentored over 30 MS/PhD students in VLSI, reconfigurable systems, and scientific computing. Collaborations & Labs Directs the ACME Lab (EE1-307), collaborating with UW Radiology (Prof. Robert Miyaoka), UW Physics (Prof. Shih-Chieh Hsu), and Drexel University (Prof. Josh Agar). Projects include quantum control systems, LHC readout electronics, and medical sensor networks.