Ioannis Sourdis is a Full Professor at the Department of Computer Engineering, Chalmers University of Technology, Sweden. His research focuses on computer architecture, reconfigurable computing, network-on-chip (NoC) design, memory systems, and fault-tolerant embedded systems, with applications in biomedical informatics and hardware security. Current projects include EUMMSS (Efficient Uncore Mechanisms for Multicore Space Systems, funded by the Swedish National Space Board) and eProcessor (European Processor Ecosystem, funded by the European Commission). Past initiatives include the DeSyRe project (on-demand system reliability), ECOSCALE (exascale reconfigurable computing), and SHARCS (secure hardware-software architectures). His work spans NoC router design (e.g., FastTrackNoC, DDRNoC), memory compression (MemSZ, L2C), and biomedical security applications (heartbeat-based protocols). He has published extensively in venues like DATE, ICS, PACT, and IEEE Transactions on Networking. Key research areas: Chiplet-based systems , hybrid memory architectures , FPGA acceleration , and real-time stream aggregation .
Sergi Abadal Cavalle is a distinguished Professor in the Department of Computer Architecture at the Universitat Politècnica de Catalunya (UPC), affiliated with the Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona (ETSETB). He leads a dynamic research group focused on revolutionary computing architectures through wireless chip-scale networks and quantum interconnects. His work is supported by prestigious grants including an ERC Starting Grant and an ERC Proof of Concept Grant. Education: PhD in Computer Architecture, Universitat Politècnica de Catalunya (2016) MSc in Telecommunication Engineering, UPC (2011) BSc in Telecommunication Engineering, UPC (2010) Sergi's research focuses on overcoming the limitations of traditional wired interconnects in computing systems by pioneering wireless communication at the chip and package level. His work spans terahertz communications, graphene-based antennas, reconfigurable metasurfaces, and quantum-coherent networks. He has led major EU projects such as WINC, EWiC, QUADRATURE, and WiPLASH, aiming to revolutionize classical and quantum computing architectures. His research integrates electromagnetics, materials science, and computer architecture to enable ultra-fast, scalable, and energy-efficient systems. His recent publications demonstrate a strong trend toward integrating wireless technologies within computing systems, particularly using novel materials like graphene and software-defined metasurfaces. The articles highlight advancements in on-chip wireless communication, channel modeling, and the application of these technologies in 6G and quantum computing. His work bridges theoretical modeling with experimental validation and practical emulation. Scientific Awards: ERC Starting Grant (2022) ERC Proof of Concept Grant (2024) ACM NanoCom Outstanding Milestone Award (2022) NanoComNet Young Investigator Award (2019) UPC Outstanding Thesis Award (2016) IN-NOVA Award to Best Master Thesis (2021) IBM Award to Best Academic Record (2021) Medal from Real Academia de la Ingeniería (2024) IEEE Senior Member (2025) Sergi actively mentors a large group of PhD and Master's students, many of whom have received awards for their thesis work. He leads the N3Cat research group and collaborates with institutions such as IBM Research, NEC Labs Europe, RWTH Aachen, EPFL, University of Nottingham, and Intel Labs. His lab is at the forefront of experimental validation of wireless interconnects and quantum architectures, with ongoing projects focusing on emulation and commercialization of chiplet communication technologies.
Mehdi Sadi is an Assistant Professor of Electrical and Computer Engineering at Auburn University's College of Engineering. He holds a Ph.D. from the University of Florida, an M.S. from the University of California-Riverside, and a B.S. from Bangladesh University of Engineering and Technology. His research focuses on secure and reliable system-on-chip design, AI/ML-driven VLSI CAD/EDA, neuromorphic hardware, and emerging post-CMOS computing technologies. Notable achievements include earning the NSF CAREER Award for chiplet-based design optimization and a $175k NSF grant for magnetic RAM research. His work integrates machine learning with hardware co-design to enhance AI accelerators' performance, energy efficiency, and security. Recent projects include adversarial attack mitigation on AI hardware and reliability analysis of neuromorphic systems. Dr. Sadi's contributions span chiplet architecture, memory systems (e.g., STT-MRAM/SOT-MRAM), and fault-tolerant computing. He actively publishes on topics like skyrmion logic gates and TRNG implementations using MRAM. His work bridges theoretical machine learning advancements with practical hardware implementations, addressing critical challenges in next-generation computing systems.
Torsten Hoefler is a Full Professor of Computer Science at ETH Zurich, Switzerland, with an adjunct appointment in Electrical Engineering. He previously held roles at the National Center for Supercomputing Applications (University of Illinois at Urbana-Champaign) and Indiana University. Full Professor of Computer Science, ETH Zurich (2020–present) Adjunct Professor of Electrical Engineering, ETH Zurich (2020–present) Member at Large, ACM SIGHPC Executive Committee (2013–present) Leadership roles in the MPI Forum and Blue Waters project His research focuses on performance-centric system design , with emphasis on scalable networking, parallel programming models, and performance modeling. Key contributions include the Slim Fly network topology, Data-Centric Python framework, and innovations in parallel graph computations and RDMA-based systems. Recent publications span topics like LLM training networks , quantization geometry , chiplet interconnects , and AI-driven climate modeling , reflecting his interdisciplinary approach combining HPC, AI, and hardware-software co-design. ACM Gordon Bell Prize (2019) ERC Consolidator Grant (2020) IEEE TCSC Award for Excellence (2019) SIAM SIAG/SC Junior Scientist Prize (2012) Latsis Prize of ETH Zurich (2015) He has received multiple best paper awards at top conferences (SC10, SC13, SC14, SC19, IPDPS'15, HPDC'15, OOPSLA'16) and contributed to MPI-3 standardization.
Kate Smith is an Assistant Professor of Computer Science at Northwestern University, affiliated with the McCormick School of Engineering. She holds a PhD in Electrical Engineering from Southern Methodist University (SMU), along with MS and BS degrees in Electrical Engineering and Mathematics from the same institution. Her research focuses on quantum computing, specifically in system architecture, optimized compilation, error mitigation, and security. Prior to joining Northwestern in 2024, she worked at Infleqtion managing the Superstaq compiler team and as a postdoctoral scholar at the University of Chicago under the CQE/IBM program. She has contributed to over 25 peer-reviewed publications and served on technical committees for major conferences like MICRO, ISCA, and DAC. Education: SMU (PhD 2019, MS 2015, BS in EE/Math 2014). Professional experience includes roles at EPFL (Switzerland), Texas Instruments, and the Darwin Deason Institute for Cyber Security. Her honors include the 2022 HPCA Best Paper Award, MIT EECS Rising Star (2021), and the IEEE TC-MVL Early Career Award (2021). Research interests span quantum compilation, distributed systems, qudit processing, and quantum security. She co-organized the 2023 CCC Workshop on Next Steps in Quantum Computing and chaired the 2022 ISMVL conference. Her work emphasizes bridging hardware-software gaps to enable scalable quantum systems. Grants and collaborations include the EPiQC group at the University of Chicago and projects funded by the Swiss NSF. Teaching experience includes courses on quantum computing fundamentals and digital design at SMU, University of Chicago, and adjunct roles.
Yu [Kevin] Cao is the Louis John Schnell Professor in the Department of Electrical and Computer Engineering at the University of Minnesota. His research focuses on microelectronics co-design for energy-efficient computing, spanning integrated circuit design, semiconductor physics, and machine learning methodologies. He leads the Microelectronics Co-design Research Group and actively collaborates with institutions like Georgia Institute of Technology, Sandia National Laboratories, and Notre Dame. His research interests include AI hardware acceleration , in-memory computing , cryogenic CMOS design , and 3D integration of heterogeneous chiplets . Current initiatives explore reconfigurable on-package systems for AI, spiking neural networks on neuromorphic hardware, and low-temperature logic technologies. Recent publications and projects highlight advancements in AI accelerators , RRAM-based compute-in-memory , graph convolutional networks , and 3D integration . His group develops tools like MN-SIM 2.0 for memristor modeling and investigates novel materials for neuromorphic systems. Grants include collaborative NSF funding for chiplet-based AI systems, CoCoSys center funding from SRC, and DOE/Sandia projects on neuromorphic hardware. Future work emphasizes scalable co-design frameworks for intelligent systems and heterogeneous integration challenges.
Alberto L. Sangiovanni-Vincentelli holds the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He is a pioneer in Electronic Design Automation (EDA) and co-founder of Cadence and Synopsys. His research focuses on Cyber-Physical Systems (CPS), embedded systems, hybrid systems, and formal methods for AI. He has authored over 800 papers and 17 books, with major contributions to design automation and methodologies. Education: Dr. Ing., EECS, Politecnico di Milano (1971) Research interests include design methodologies, CPS, and AI integration. He has received numerous awards, including the IEEE James Clerk Maxwell Medal (2008) and ACM/IEEE A. Richard Newton Technical Impact Award (2009). He serves on multiple corporate boards and advisory councils, including the Strategic Committee of the Italian Strategic Fund and the Executive Committee of the Italian Institute of Technology. His work spans academia, industry, and policy, with a focus on innovation ecosystems and CPS design automation. Awards: Over 20 major honors, including Fellowships from IEEE and ACM.
Alessandro Fogli is a PhD Student at Imperial College London in the Department of Computing, affiliated with the Large-Scale Data & Systems (LSDS) Group . His research focuses on systems support for data analytics in cloud environments, including distributed systems, resource management, and query processing. Education PhD in Computer Science, 2019–Present, Imperial College London MSc in Computer Science, 2015–2017, Roma Tre University BSc in Computer Science, 2012–2015, Roma Tre University His research spans Distributed Systems , Databases , Data Analytics , and Modern Hardware . Recent work examines chiplet-based processor architectures and runtime mapping systems, with applications in performance optimization and hardware-aware query execution. Scientific Contributions Co-developed CHARM (2025), a runtime mapping system for chiplet heterogeneity Published in VLDB (2024) on OLAP processing for chiplet-based CPUs Contributed to HeatWave at Oracle Labs, improving query offloading to in-memory accelerators
Peipei Zhou is an Assistant Professor of Engineering at Brown University's School of Engineering, serving as Concentration Advisor for Computer Engineering. Her work bridges computer science and engineering across hardware, abstraction layers, and software outputs. Her research spans critical computing domains: Electronic design automation and computer architecture Reconfigurable and heterogeneous computing systems Compiler optimization and modeling for computing systems Chiplet-based architectures and sustainable computing Applications in precision medicine and artificial intelligence Professor Zhou mentors students through her Computer Engineering concentration advising role, focusing on hardware-software co-design to advance computing efficiency and medical applications.
Shuang Liu is a Researcher at the Institute of Computer Architecture and Computer Engineering, University of Stuttgart. Their work focuses on embedded systems, networks-on-chip (NoC), and chip design methodologies. They specialize in deadlock-free routing, fault-tolerant computing, and application-specific system synthesis using advanced techniques like integer linear programming. Research interests include optimizing NoC architectures for chiplet-based systems, co-design of floorplanning and routing topologies, and energy-efficient signal processing in medical electronics. Their recent work emphasizes formal verification methods and performance optimization in hardware-software co-design. Publications span topics such as deadlock prevention in NoC, ILP-based routing synthesis, and trade-offs in hearing aid ASIP design. Office hours are Monday 2–3 p.m. in Room 1.001, Pfaffenwaldring 5b, Stuttgart.
Harald Pretl is a Professor at the Department of Integrated Circuits within the Institute for Integrated Circuits and Quantum Computing at Johannes Kepler University Linz (JKU). Holding the title Univ.-Prof., he maintains active research leadership with current projects extending through 2029 and 107 documented research outputs including patents, articles, and conference proceedings. His research spans integrated circuits, quantum computing, mm-wave transmission, biomedical sensing, and open-source EDA tools. He specializes in high-frequency circuit design, ultra-low-power biomedical sensors, and educational applications of open-source design methodologies for analog/mixed-signal IC development. Recent work demonstrates cross-disciplinary innovation bridging engineering, neuroscience, and artistic expression. Recent publications reveal strong emphasis on practical implementation challenges: THz transmitter efficiency, brain-computer interface applications, ADC performance metrics, and open-source layout automation. These works collectively advance wireless communication systems, biomedical instrumentation, and accessible semiconductor design education through open-toolchain development. Prof. Pretl has supervised 3 students and actively promotes open-source EDA adoption through educational initiatives. His funded projects include Sub-blocks generators for NSSAR ADC (2025-2029), Open Parasitic Extraction for KLayout, and United Micro Technology collaborations, demonstrating sustained industry engagement. He co-leads the JKU LIT - SAL Intelligent Wireless Systems Lab (IWS Lab) and contributes to the High-Performance Integrated Quantum Computing project. Current activities include 42 documented presentations such as 'Using Open-Source EDA Tools in Hands-On IC Design Education' (2025) and 'Recent Developments in Ultra-Low-Power Biomedical Sensing' (2025), reflecting his dual focus on research innovation and pedagogical advancement.
Ozgur Sinanoglu is a Professor of Electrical and Computer Engineering at New York University Abu Dhabi (NYUAD) and a Global Network Professor at NYU Tandon School of Engineering. He holds a B.S. in Electrical and Electronics Engineering and Computer Engineering from Bogazici University (1999), and an M.S. and Ph.D. in Computer Science and Engineering from UC San Diego (2001, 2004). His research focuses on hardware security, design-for-trust, and VLSI circuit reliability. Education: B.S., Electrical and Electronics Engineering & Computer Engineering, Bogazici University, 1999 M.S., Computer Science and Engineering, UC San Diego, 2001 Ph.D., Computer Science and Engineering, UC San Diego, 2004 Research Interests: Design-for-Security in VLSI circuits Logic locking and hardware obfuscation Hardware Trojans and side-channel attacks Secure chip manufacturing and testing His work has led to over 200 publications and 20 patents. He directs the NYUAD Center for Cybersecurity and the Design-for-Excellence Lab, funded by NSF, DoD, Intel, and Mubadala Technology. Awards include the NYUAD Distinguished Research Award (2021) and induction into the UAE's Mohammed bin Rashid Academy of Scientists (2021). Grants and Leadership: Lead PI on NSF and DoD-funded projects Directed ACM ASIACCS 2017 in Abu Dhabi Associate Editor for IEEE TIFS, TETC, and JETC Labs and Teams: Center for Cybersecurity (CCS) Design-for-Excellence Lab (DfX)
Yakun Sophia Shao is an Associate Professor in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. She holds a Ph.D. (2016) and M.S. (2014) in Computer Science from Harvard University, alongside a B.E. in Electrical Engineering from Zhejiang University, China. Her research focuses on computer architecture , particularly domain-specific accelerators , heterogeneous systems , and agile VLSI design methodologies . Key research centers: Agile Design of Efficient Processing Technologies (ADEPT), Berkeley Emerging Technologies Research (BETR), Berkeley Wireless Research Center (BWRC), SpeciaLIzed Computing Ecosystems (SLICE) Her work explores hardware-software co-design for efficiency in AI and robotics, including projects like Simba (chiplet-based AI accelerators) and Virgo (GPU matrix units). Notable tools developed include WIICA (workload characterization) and Chipyard (SoC frameworks). Selected honors include: 2024 CRA-WP Anita Borg Early Career Award 2023 NSF CAREER Award 2022 IEEE TCCA Young Computer Architect Award 2022 Intel Rising Star Faculty Award She teaches courses including EECS 151 (Digital Design & ICs) and EECS 251A (Advanced Digital Design).
Prof. Dr. Jana Giceva is a Professor for Database Systems at the TUM School of Computation, Information and Technology since 2020. Her research bridges database systems with modern computer architecture, focusing on hardware-aware data processing, operating system integration, and efficient execution of big data workloads. She previously held roles at Imperial College London, Microsoft Research, and Oracle Labs. Education: PhD in Computer Science from ETH Zurich (2017) Awards: ERC Starting Grant (2024), ETH Medal (2018), VMware Early Career Faculty Award (2019), Google PhD Fellowship (2014) Her work explores database/operating system co-design , chiplet-aware scheduling , and disaggregated systems programming , with publications covering query optimization, graph data structures, and hardware acceleration. Collaborations with institutions like Imperial College London and ETH Zurich highlight her cross-disciplinary impact. Key Research Themes: Hardware-Software Integration High-Performance Query Execution Asynchronous I/O Optimization Adaptive Runtime Systems
James Buckwalter is a Professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. His research focuses on high-speed mixed-signal circuits, RF and millimeter-wave integrated systems, RF photonic interfaces, and optoelectronic integration using CMOS and III-V technologies. PhD: California Institute of Technology MS: University of California, Santa Barbara BS: California Institute of Technology His research explores heterogeneous integration of RF transistor chiplets, millimeter-wave power amplifiers, and energy-efficient optical communication systems. Recent work includes D-band and G-band circuit design, coherent optical links for data centers, and advanced packaging techniques. His 15 most recent publications (2024-2025) focus on millimeter-wave CMOS and III-V ICs, optical transceivers, and heterogeneous integration methods. Key trends include energy-efficient communication systems, DSP-free architectures, and high-frequency amplifier optimization. IEEE Fellow IEEE TMTT Young Engineer Award NSF Early Career Development Award DARPA Young Faculty Award IBM PhD Fellowship He leads the RF & Mixed-signal Integrated Systems Laboratory, which investigates radio-frequency CMOS, millimeter-wave ICs, optoelectronic transceivers, and software-defined radio technologies.
