Per Stenstrom

Per Stenstrom is a Professor of Computer Engineering at Chalmers University of Technology, Sweden since 1995. His research focuses on computer architecture, particularly high-performance memory systems and energy-efficient computing. He has authored/co-authored four textbooks, over 200 publications, 20 patents, and supervised approximately 25 PhD students.

• Awarded ACM Fellow and IEEE Fellow.
• Member of Academia Europaea and the Royal Swedish Academy of Engineering Sciences.
• Co-founder of the HiPEAC Network of Excellence.
• Served as Editor or Associate Editor for journals like ACM Transactions on Architecture and Code Optimization and IEEE Transactions on Computers.
• Program Chair for major conferences including ISCA, HPCA, IPDPS, and ACM International Conference on Supercomputing.

His research innovations include cache compression techniques, memory optimization strategies, and energy-aware resource management in multicore systems. Ongoing work emphasizes secure and scalable cache partitioning, hybrid memory systems, and defense mechanisms against microarchitectural attacks.