Darryl Veitch

Darryl Veitch is a Professor in the School of Electrical and Data Engineering at the University of Technology Sydney (UTS), affiliated with the Global Big Data Technologies Centre. He holds a PhD in Mathematics from the University of Cambridge (1990) and a BSc (Hons) from Monash University (1985). His research focuses on computer networking, including traffic modeling, parameter estimation, active measurement, and clock synchronization over networks. A Fellow of the IEEE, he has held academic positions globally, including as a Professorial Research Fellow at the University of Melbourne (2000–2014).

• Education:
  • PhD in Mathematics, University of Cambridge, 1990
  • BSc (Hons) in Mathematics, Monash University, 1985
• Key Roles:
  • Professor at UTS since 2015
  • Professorial Research Fellow at University of Melbourne (2000–2014)

His research interests span network timing, security, and measurement methodologies. Notable contributions include work on leap second implications for global timing systems and robust synchronization protocols. He has authored over 176 research outputs and contributes to academic leadership through conference organization and editorial roles.

Awards: Fellow of the IEEE (recognized for contributions to network measurement and synchronization).

Teaching & Supervision: Specializes in Computer Networking, Signal Processing, and Information Theory. Taught subjects like Transmission Systems (2016) and Web Systems (2018–present).

Labs/Teams: Active contributor to UTS’s Global Big Data Technologies Centre, focusing on scalable network measurement and timing infrastructure.