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Conor RyanView profile

Professor

• Genetic Programming
• Genetic Algorithms
• Grammatical Evolution
• +7 more

Conor Ryan is a Professor in the Department of Computer Science & Information Systems at the University of Limerick. He is a Science Foundation Ireland-funded Investigator since 2002 and a member of multiple research centres including Lero – the Irish Software Research Centre and the Limerick Digital Cancer Research Centre. His research focuses on Genetic Programming, Grammatical Evolution, and their applications in domains like healthcare analytics, digital circuit design, and financial modeling. He has authored over 250 publications, with recent work emphasizing automated feature selection in medical diagnostics, neural architecture search, and blockchain ecosystems. Teaching includes courses on Foundations of Computer Science and Computer Games Programming. Research interests span evolutionary computation, machine learning, and interdisciplinary applications. Collaborations involve global institutions, reflecting his work's impact across computer science, engineering, and healthcare. His research has addressed challenges in breast cancer diagnosis via genetic algorithms, cryptocurrency volatility prediction using random forests, and automated generation of digital circuits. Ongoing projects explore interpretability in AI, energy-efficient computing, and sustainable transport systems through predictive analytics. Professional memberships include roles in the Centre for Research Training in Foundations of Data Science and the Data-Driven Computer Engineering Research Centre, underscoring his commitment to interdisciplinary innovation.

• Network Security
• Android Security
• Malware Analysis
• +6 more

Vijay Laxmi is a Professor in the Department of Computer Science and Engineering at Malaviya National Institute of Technology (MNIT) Jaipur, India. With over a decade of active research publication from 2014-2024, Dr. Laxmi has established themselves as a prominent researcher in network security, Android security systems, and Network-on-Chip architectures. Their work demonstrates consistent collaboration with Manoj Singh Gaur and numerous doctoral students at MNIT Jaipur. Dr. Laxmi's research interests span Network Security, Android Security, Malware Analysis, Network-on-Chip Architectures, Routing Protocols, Side-Channel Attacks, Wireless Networks, and Mobile Security. Their work bridges theoretical security frameworks with practical implementations, particularly in mobile and embedded systems. Recent publications indicate a growing focus on AI-based security approaches including GAN applications for fuzzing and deep learning for image dehazing. The research trajectory shows increasing sophistication in security analysis techniques, evolving from basic malware detection to advanced side-channel attack analysis and sophisticated network security protocols. Recent publications demonstrate expertise in both theoretical frameworks and practical implementations with applications in real-world security challenges. Dr. Laxmi has mentored numerous graduate students including Vineeta Jain, Anugrah Jain, Sonal Yadav, Mohit Singh, and Gaurav Singal, who appear as co-authors across multiple publications. Their collaborative network extends to researchers at international institutions, indicating strong academic connections beyond their home institution.

Hailong JiaoView profile

Assistant Professor

• low-power VLSI circuit design
• variations-resilient systems
• error-resilient systems
• +10 more

Hailong Jiao is an Assistant Professor in the Department of Electrical Engineering at Eindhoven University of Technology (TU/e) and an Associate Professor at Peking University Shenzhen Graduate School's School of Electronic and Computer Engineering. He is also a Visiting Assistant Professor with TU/e's Electronic Systems group. His research focuses on low-power and variations-resilient VLSI circuit and system design , including error-resilient systems, approximate computing, machine learning in VLSI, ultra-low voltage circuits, and emerging devices like 3D integration and carbon electronics. Education : BSc (highest honor, 2004, Shandong University), MSc (2008, Institute of Microelectronics, Chinese Academy of Sciences), PhD (2012, HKUST). Collaborations : BrainWave project (TU/e and Radboud University Nijmegen) developing wearable brainwave processing for epilepsy/Parkinson's healthcare. Editorial Roles : Associate Editor for Elsevier Microelectronics Journal and World Scientific Journal of Circuits, Systems, and Computers. Committee Memberships : HiPEAC, MemoCiS, ACM/SIGDA, and six IEEE committees. Research Trends : Recent articles emphasize energy-efficient IoT networks , voltage stacking , sensitivity control , and scan flip-flop design , aligning with UN SDGs for energy engineering and healthcare innovation. Scientific awards include highest honor at BSc .

Suman DattaView profile

Professor

• Semiconductor Devices
• Nanotechnology
• VLSI Systems
• +7 more

Suman Datta is a Professor at the Georgia Institute of Technology , holding the Joseph M. Pettit Chair in Advanced Computing and Georgia Research Alliance Eminent Scholar titles. He has a joint appointment with the School of Materials Science and Engineering. Education : B.Tech in Electrical Engineering from IIT Kanpur; Ph.D. in Electrical and Computer Engineering from the University of Cincinnati. Prior Appointments : Stinson Endowed Chair Professor of Nanotechnology at University of Notre Dame (2015–2022); Professor at Penn State (2007–2015); Intel Corporation (1999–2007) in Advanced Transistor Group. Research Interests : His work focuses on high-performance heterogeneous computing using advanced CMOS and beyond-CMOS semiconductors. Key areas include ferroelectric field-effect transistors (FeFETs) , cryogenic computing , in-memory computing , and brain-inspired computing . He explores materials like ferroelectric gate stacks , insulator-to-metal phase transition oxides , and high-mobility oxides for next-generation compute architectures. Recent Article Trends : His group’s publications emphasize BEOL-compatible oxide transistors , negative capacitance , radiation-resilient devices , and machine learning-aided modeling . Subfields include low-voltage memory , 3D Ising machines , dynamic logic at cryogenic temperatures , and monolithic integration of power delivery systems. Scientific Awards : IEEE Fellow (2013) for contributions to transistor technologies NAI Fellow (2016) for societal impact via patents Intel Achievement Award (2003) for high-k/metal gate CMOS Intel Logic Technology Quality Award (2002) for Tri-gate transistors SEMI Award (2012) for high-k dielectrics Penn State Outstanding/ Premier Research Awards (2012, 2015) Advising & Grants : He has mentored students like Wriddhi Chakraborty , Khandker Akif Aabrar , and Sourav Dutta . His research is funded by SRC , DARPA , and NSF , including leadership of the ASCENT and EXCEL centers. Labs & Collaborations : Datta directs the STAR Lab at Georgia Tech, which specializes in atomistic modeling , nanofabrication , and compact model development . The lab collaborates with industry giants like Intel , Micron , and IBM through the ASCENT center.

Tobi DelbruckView profile

Professor

• Neuromorphic Engineering
• Event-Based Vision Systems
• Silicon Retinas
• +6 more

Tobi Delbruck is a titular professor of physics and electrical engineering at ETH Zurich, where he leads the Sensors Group at the Institute for Neuroinformatics (INI) in Zurich, Switzerland. He collaborates closely with Shih-Chii Liu and Giacomo Indiveri as part of the 'hardware groups' at INI. Delbruck has also served as visiting faculty at Caltech and is a Fellow of the IEEE. His work focuses on bio-inspired and neuromorphic event-based sensory processing systems. Professor Delbruck's research spans multiple areas of neuromorphic engineering, with particular emphasis on event-based vision systems and low-power analog VLSI circuits. His work has significantly advanced the field of Dynamic Vision Sensors (DVS), which mimic the human retina's response to changes in brightness rather than capturing full frames. This approach enables extremely low-latency vision processing with minimal power consumption, making it ideal for high-speed applications and robotics. His research has applications in robotics, autonomous systems, and low-power embedded vision. Delbruck is an active contributor to the neuromorphic engineering community, co-organizing the annual Telluride Workshop on Neuromorphic Engineering and serving in leadership roles with IEEE. He has authored numerous influential publications and co-authored books including "Event-Based Neuromorphic Systems" and "Analog VLSI: Circuits and Principles." His jAER (Java Address-Event Representation) project provides open-source tools for real-time event-based sensory processing. Analysis of his recent publications shows a clear trend toward integrating event-based vision with deep learning techniques and applying these systems to practical robotics problems. His scientific achievements have been recognized with multiple awards including: IEEE Fellow Winner of Best Live Demonstration award at ISCAS 2012 Honorable Mention Award from Sensory Systems Technical Committee at ISCAS 2012 Overall Best Student Paper Award and Best Paper Award from Sensory Systems Technical Committee at ISCAS 2010 Winner of the 2006 ISSCC Jan Van Vessem Outstanding European Paper Award Professor Delbruck actively mentors students and has supervised numerous PhD and Master's theses in the areas of neuromorphic engineering and event-based vision systems. His group has secured significant research funding from various sources to support their innovative work in bio-inspired sensory processing. He teaches courses on "Electronics for Physicists II (Digital)" and "Neuromorphic Engineering," helping to train the next generation of researchers in this field. The Sensors Group at INI, which Delbruck leads, operates state-of-the-art facilities for designing and testing neuromorphic vision systems. The group maintains close collaborations with researchers worldwide and has developed several important open-source resources including the jAER project and bias generator design kits. Their work continues to push the boundaries of what's possible with event-based sensory processing, with applications ranging from high-speed robotics to low-power embedded vision systems.

Bharat BhuvaView profile

Professor

• Computer-Aided Design
• Radiation Effects on Electronics
• Semiconductor Device Modeling
• +3 more

Professor Bharat Bhuva is a faculty member in the School of Engineering at Vanderbilt University, holding the position of Professor of Electrical Engineering and Computer Engineering . His research focuses on radiation effects on integrated circuits, semiconductor device modeling, and VLSI design, with an emphasis on advancing the resilience of nanoscale electronics against single-event effects and total-ionizing-dose damage. He also investigates emerging technologies like FinFET and FDSOI for improved radiation hardness and performance. Education: Ph.D. in Electrical Engineering, North Carolina State University M.S. in Electrical Engineering, North Carolina State University B.S. in Electrical Engineering, Maharaja Sayajirao University Research Interests: Professor Bhuva’s work spans computer-aided design tools, semiconductor process modeling, and the mitigation of radiation-induced failures in advanced integrated circuits. His studies address challenges posed by scaling to smaller technology nodes (e.g., 3-nm FinFET) and the impact of environmental factors like temperature, bias conditions, and neutron exposure on circuit reliability. Key areas include multicell upsets, single-event upset (SEU) cross-section analysis, and the efficacy of radiation-hardened-by-design (RHBD) techniques. Awards & Recognition: None explicitly listed in the provided text. However, his extensive publications in top-tier journals like IEEE Transactions on Nuclear Science highlight his contributions to the field. Grants & Advising: Advises on projects related to advanced semiconductor technologies and radiation effects. His research has been supported by grants from institutions focusing on space electronics and nanotechnology. No specific grant details or student advisees are listed. Labs & Teams: Likely affiliated with Vanderbilt’s Cyber-physical Systems and Nano Science and Technology research neighborhoods, though specific lab names are not mentioned in the text.

Jason CongView profile

Professor

• Electronic Design Automation
• VLSI CAD
• FPGA Synthesis
• +6 more

Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.

• Microelectronics
• Nanotechnology
• RF Engineering
• +3 more

Prof. Dr. Amelie Hagelauer holds a professorship in Micro- and Nanosystem Technology at the TUM School of Computation, Information and Technology, Technical University of Munich. Her work focuses on advanced electronics and systems integration across quantum computing hardware, resistive memory technologies, and high-frequency RF systems. She has contributed to innovations in superconducting qubit readout architectures, multi-level RRAM designs, and 3D-integrated CMOS-compatible quantum devices. Research interests span quantum hardware design, nanoelectronic devices, RF front-end systems, and emerging memory technologies. Her work emphasizes practical implementation challenges such as low-power operation, high-voltage handling in RF switches, and wafer-scale fabrication processes. Recent projects include D-band radar systems, energy-efficient 60 GHz transceivers, and antenna tuning solutions for 5G applications. Publications from 2023-2025 showcase advancements in resistive switching device characterization, mitigation of TLS losses in superconducting qubits, and reconfigurable AI accelerators using RRAM-based digital twins. Her work bridges theoretical device physics with practical integrated circuit design, addressing scalability and reliability in next-gen electronics. Awards and grants: None explicitly listed in provided texts. Active collaborations include EU-funded projects on quantum computing platforms and TUM's Electronic Photonic Integration initiatives. Leads research teams in microsystem technology with emphasis on cross-disciplinary approaches combining CMOS processes, MEMS, and quantum engineering.

Callie HaoView profile

Assistant Professor

• Software/Hardware Co-design
• Reconfigurable Computing
• Graph Computing
• +5 more

Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.

• integrated system design
• quantum computation
• information security
• +4 more

Nozomu Togawa is a Professor at Waseda University's Faculty of Science and Engineering, School of Fundamental Science and Engineering, specializing in Computer Science. He has held this position since 2009 and also serves as Chief Scientific Officer (CSO) of Quanmatic Inc. since 2022. With a PhD in Engineering from Waseda University (1997), his academic journey includes positions at Waseda University and the University of Kitakyushu before his current professorship. His research interests focus on integrated system design , quantum computation , and information security . Togawa has published extensively with over 368 papers and significant citation metrics (Scopus h-index: 23, Google Scholar h-index: 28). His work bridges theoretical quantum computing with practical security applications, particularly in hardware security and IoT systems. Togawa's research demonstrates a clear progression from traditional hardware security toward quantum-inspired computing solutions. His recent publications focus on Ising machines, quantum annealing, and hardware Trojan detection, showing how quantum approaches can solve complex optimization problems in security contexts. He has made significant contributions to applying quantum computing techniques to practical problems like course selection optimization, travel planning, and hardware security verification. Among his notable recognitions are the Minister of Education, Culture, Sports, Science and Technology Award for Science and Technology (2018), SCOPE Results Development Promotion Award (2022), and multiple Best Paper Awards. He serves on important committees including the Ministry of Internal Affairs and Communications Cyber Security Task Force and the Institute of Electronics, Information and Communication Engineers' VLSI Design Technology Research Committee. Togawa actively mentors students who frequently appear as co-authors on his publications. His research group produces high-impact work in quantum computing applications and hardware security, with strong industry connections through his CSO role at Quanmatic Inc. He has received substantial research funding supporting his innovative work at the intersection of quantum computing and security.

Shantanu DuttView profile

Professor

• VLSI CAD
• Discrete Optimization
• FPGA Testing and Trusted Design
• +2 more

Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.

Brandon ReagenView profile

Assistant Professor

• Computer Architecture
• Hardware Acceleration
• Machine Learning
• +3 more

Brandon Reagen is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University's Tandon School of Engineering, with affiliations in Computer Science, the Center for Advanced Technology in Telecommunications (CATT), and the NYU Center for Cybersecurity (CCS). He holds a PhD in Computer Science from Harvard (2018) and undergraduate degrees in Computer Systems Engineering and Applied Mathematics from the University of Massachusetts, Amherst (2012). His research focuses on computer architecture, hardware acceleration for deep learning and privacy-preserving computation, and VLSI design. He pioneered efficient deep learning accelerator designs through unsafe optimizations and contributed to benchmarking frameworks like Aladdin and MachSuite. His work spans privacy-preserving machine learning, secure computing systems, and hardware-software co-design for cryptographic protocols. Key achievements include the NSF CAREER Award (2024) and Siebel Scholar recognition (2018). His research centers on advancing secure computing through innovations like zero-knowledge proof accelerators (e.g., zkSpeed), fully homomorphic encryption frameworks (Orion), and entropy-guided privacy techniques for large language models. He leads interdisciplinary efforts at CATT and CCS to bridge hardware design and cybersecurity challenges. Reagen's contributions include over 50 publications in top-tier conferences (e.g., ISCA, ASPLOS, MLSys) and industry collaborations at Facebook AI. His work emphasizes practical solutions for encrypted computation efficiency, privacy-preserving inference, and scalable secure systems.

Azad J NaeemiView profile

Professor

• Nanotechnology
• Nanoelectronics
• Spintronics
• +5 more

Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.

Jiang HuView profile

Professor

• VLSI Design Automation
• Hardware Security
• Machine Learning Applications
• +3 more

Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.

Jing LiView profile

Associate Professor

• Computer Architecture
• Compiler Design
• Distributed Systems
• +7 more

Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.