Shantanu Dutt

Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago, located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu.

Education

• Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990)
• M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984)
• B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983)

Research Interests

Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD), with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design, ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance.

Scientific Awards

• 1996 Best Paper Award, ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning”
• 1995 Most Influential Paper Award, Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures”

Research Impact and Funding

Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies.

Laboratory and Collaborations

Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.