Azad J Naeemi

Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI).

His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008).

Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education.

Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes.

His scientific honors include:

• IEEE Solid-State Circuits Society James Meindl Innovators Award (2022)
• IEEE Electron Devices Society Paul Rappaport Award (2008)
• NSF CAREER Award (2013)
• SRC Inventor Recognition Award (2010)
• Multiple Georgia Tech teaching awards

Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013).

His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.