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Naresh R. ShanbhagView profile

Professor

• Energy-efficient computing
• Machine learning hardware
• In-memory computing
• +7 more

Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.

Morteza FayaziView profile

Assistant Professor

• Electronic Design Automation (EDA)
• Machine Learning (ML) in Analog Circuit Design
• System-on-Chip (SoC) Design Automation
• +3 more

Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.

Stephen W. KecklerView profile

Adjunct Professor

• Computer Architecture
• Deep Learning Accelerators
• GPU Computing
• +4 more

Stephen W. Keckler is an Adjunct Professor at the Department of Computer Science , The University of Texas at Austin , and serves as Vice President of Architecture Research at NVIDIA . He is an ACM Fellow , IEEE Fellow , and Sloan Foundation Research Fellow . Education: BS in Electrical Engineering, Stanford University (1990) SM in Computer Science, Massachusetts Institute of Technology (1992) PhD in Computer Science, MIT (1998) Research Interests focus on computer architecture for deep learning , GPU computing , and energy-efficient systems . His work explores memory compression , network-on-chip designs , and heterogeneous computing . Publication Trends highlight advancements in deep learning accelerators , GPU memory systems , and energy-efficient architectures . Notable themes include sparsity exploitation , multi-chip modules , and fault-tolerant GPU pipelines . Scientific Recognition : ACM Fellow IEEE Fellow Sloan Foundation Research Fellow Best Paper Awards at ASPLOS 2009 and ISPASS 2011 Laboratory Affiliations : Computer Architecture and Technology Laboratory (CART) TRIPS Project (Tera-Op Reliable Intelligently adaptive Processing System) NVIDIA Research

Austin RovinskiView profile

Assistant Professor

• Computer Architecture
• VLSI
• Electronic Design Automation (EDA)
• +5 more

Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.

Ameer AbdelhadiView profile

Assistant Professor

• Hardware Acceleration
• Neurotechnology
• Reconfigurable Computing
• +4 more

Dr. Ameer Abdelhadi is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on application-specific custom-tailored computer architectures, hardware-efficient deep learning, neurotechnology, and reconfigurable computing. He holds a PhD from the University of British Columbia and has held academic positions at the University of Toronto, Imperial College London, and Simon Fraser University, alongside industry experience in semiconductor design. Education: PhD in Computer Engineering (University of British Columbia, 2016). Research Interests: Hardware acceleration for machine learning and neurotechnology Reconfigurable computing and FPGAs/ASICs Asynchronous circuits and synchronization protocols VLSI physical design and CAD algorithms Publications span high-impact venues such as IEEE Journal of Solid-State Circuits, IEEE Hot Chips, and IEEE Micro. Notable achievements include the 2017 Best Paper Award at ASYNC for work on synchronization FIFOs. Teaching includes COMPENG 4DV4 (VLSI System Design) and ELECENG 4OI6B (Engineering Design). His lab focuses on advancing hardware systems for next-generation applications in AI and biomedical engineering.

David Zhigang PanView profile

Professor

• Electronic Design Automation
• Machine Learning
• Hardware Acceleration
• +5 more

David Zhigang Pan is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He also holds the Silicon Laboratories Endowed Chair. Prior to joining UT Austin, he was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His academic journey began with a B.S. from Peking University, followed by M.S. and Ph.D. degrees from UCLA. Research Areas: Electronic Design Automation (EDA), Machine Learning Hardware, FPGA Prototyping, Optical Computing, Hardware Security, and CAD for Emerging Technologies Academic Timeline: Assistant Professor (2003-2008), Associate Professor (2008-2013), Full Professor (2013-present) His research focuses on design automation for mixed-signal circuits , GPU-accelerated EDA tools , and hardware-software co-design for AI . Recent work explores FFT-based optical neural networks and deobfuscation techniques for integrated circuits , reflecting his interdisciplinary approach at the intersection of machine learning , computer architecture , and semiconductor manufacturing . Key publication trends reveal expertise in: VLSI design , lithography optimization , and deep learning applications for EDA tools. His work has been recognized with multiple Best Paper Awards at top conferences including DAC , ASP-DAC , and HOST . Awards: IEEE Fellow (2014), SPIE Fellow (2017), ACM SRC Graduate Category Honors for students Patents: 8 U.S. Patents in electronic design and hardware optimization Prof. Pan has mentored 40 PhDs and postdocs who now hold key positions in academia and industry. He leads research initiatives involving GPU acceleration frameworks and optical computing architectures . His lab focuses on vertical integration of architecture, CAD tools, and fabrication technologies for next-generation hardware solutions.

• Electrical and Computer Engineering laboratory curriculum
• Digital systems design
• CAD for VLSI
• +4 more

Mark C. Johnson is a Senior Lecturer at the Elmore Family School of Electrical and Computer Engineering at Purdue University, West Lafayette. He serves as Director of Instructional Laboratories and Associate Director for Design - Semiconductor Degree Program , overseeing laboratory infrastructure, CAD software administration, and curriculum development for courses like ECE337, ECE437, and ECE364. Education: Ph.D. in Electrical Engineering (1998), Purdue University M.S. in Electrical Engineering (1991), Wichita State University B.S. in Electrical Engineering (1983), Purdue University - Calumet His research focuses on electrical and computer engineering laboratory curriculum innovation , digital systems design , and CAD for VLSI . Over 15 recent publications highlight his work in SoC prototyping , low-power circuit design , and educational technology , spanning projects like FPGA filter optimization, dual-core processor experiments, and active learning strategies. Leadership Roles: Proceedings Chair (2003), MSE Program Chair (2005), MSE General Chair (2007), MSE Steering Committee Member, MSE & European Workshop on Microelectronics Education Chair, ECE Instructional Innovation Group (2004-2012) Secretary/Webmaster, ASEE Illinois/Indiana Section (2002-2011) He directs the ECE437 Computer Architecture Prototyping Lab and System on Chip Extension Technologies (SoCET) team , and co-advises the STARS semiconductor readiness program. Outside academia, he is an organist at Faith Presbyterian Church and composes keyboard music.

Albert H. TitusView profile

Professor

• Wearable Sensors
• Biosensors
• Bioinstrumentation
• +5 more

Albert H. Titus is a Professor in the Department of Biomedical Engineering and an Adjunct Professor in the Department of Electrical Engineering at the University at Buffalo, State University of New York. He serves as Associate Vice President for Regulatory Support in the Office of the Vice President for Research and Economic Development. His research focuses on analog VLSI design for neuromorphic visual processing, biosensors, wearable devices, optoelectronic systems, and neural networks. Education: PhD in Electrical and Computer Engineering, Georgia Institute of Technology (1997) MS in Electrical Engineering, University at Buffalo (1991) BS in Electrical Engineering, University at Buffalo (1989) Research Interests: His work spans wearable and implantable sensors, bioinstrumentation, neural network-based visual processing, analog VLSI implementations, optoelectronics, and electronic packaging. He pioneered CMOS-based neuromorphic systems and developed patented technologies for glare sensing and RF power calorimetry. Publication Trends: His recent articles emphasize CMOS-integrated sensors, machine learning for bioimpedance analysis, implantable medical devices, and xerogel-based optical biosensors. These works bridge biomedical engineering and microelectronics. Scientific Recognition: He is a Fellow of the National Academy of Inventors and has received the SUNY Chancellor’s Award for Excellence in Service (2017), NSF CAREER award, and Western New York Inventor of the Year (2010). His inventions include a patented low-power glare sensor (U.S. Patent 7,586,079) featured in Popular Science’s 2011 Top Ten Inventions. Academic Leadership: As a faculty member, he has supervised nearly 20 PhD and over 40 MS students, while teaching courses in circuits, IC design, sensors, and signal processing across electrical and biomedical engineering disciplines.

Manolis G.H. KatevenisView profile

Professor

• Computer Architecture
• VLSI Systems
• Interconnection Network Architecture
• +4 more

Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and Deputy Director and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research & Technology - Hellas (FORTH). He co-founded the European Research Center on Computer Architecture (EuReCCA) and is a founding partner of the European Network of Excellence on High-Performance and Embedded Architecture and Compilation (HiPEAC). PhD in Computer Science from University of California, Berkeley (1983) Co-founder of EuReCCA (2011) Contributed to RISC architecture (1980-1983), interconnection networks (1985-2011), and parallel computing (1993-2010) His research spans Scalable Multicore Systems , Interconnection Network Architecture , Packet Switch Design , Computer Architecture , and VLSI Systems . He has made foundational contributions to per-flow queueing, backpressure mechanisms, and wormhole IP over ATM, with applications in internet routers, data centers, and supercomputers. His publications focus on high-radix crossbar switches, flow control algorithms, and explicit interprocessor communication. Notable scientific awards include: ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981-1983) Greek State Fellowship (1973-1978) He has supervised 40 graduate theses and participated in 22 R&D projects totaling €9M, including HiPEAC (coordinator of interconnection networks), SARC (FPGA prototype design), and ENCORE (cache-optimized remote DMA). His work has received over 2000 citations, with an h-index of 23.

• CAD tools
• Digital architectures
• Emerging technologies
• +9 more

Giovanna Turvani is an Associate Professor at the Department of Electronics and Telecommunications (DET) at Politecnico di Torino, with affiliations in both the College of Electronic, Telecommunications and Physics Engineering and the College of Computer, Film, and Mechatronics Engineering. Scientific Branch: IINF-01/A - Electronics ERC Sectors: PE7_4, PE7_11, PE6_1, PE6_14, PE7_3 SDG Goals: Quality Education, Gender Equality, Affordable Energy, Industry Innovation Her research focuses on advanced electronics and quantum technologies, including: Logic-in-memory computing Quantum computing architectures Microwave imaging for medical and agricultural applications CAD tools for emerging nanotechnologies Embedded systems for bee health monitoring IoT solutions for bio-waste valorization Publications show strong expertise in quantum computing, nanocomputing, and microwave imaging, with recent trends emphasizing quantum optimization frameworks, in-memory architectures, and IoT-based agricultural technologies. She supervises PhD students in areas like quantum machine learning algorithms, predictive on-board systems, and quantum hardware design. Collaborations span multiple disciplines, including medical device development and agricultural electronics. Patents include innovations in microwave imaging, racetrack memory logic functions, and in-memory computing devices.

Marc ReichenbachView profile

Professor

• Integrated Circuits
• Embedded Systems
• VLSI Design
• +7 more

Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.

Shimeng YuView profile

Professor

• Semiconductor Devices
• Non-Volatile Memories
• 3D Integration
• +5 more

Shimeng Yu is a full professor at the Georgia Institute of Technology's School of Electrical and Computer Engineering, holding the Dean’s Professorship. He earned his B.S. from Peking University (2009) and M.S./Ph.D. from Stanford University (2011/2013). His research focuses on semiconductor devices, non-volatile memories, 3D integration, and AI hardware accelerators. Yu leads SRC/DARPA JUMP 2.0 centers on memory/storage and 3D integration, with over 400 publications and 30,000+ citations (H-index 82). He serves on flagship conference committees (e.g., IEDM, VLSI) and editorial boards (IEEE EDL, JETCAS). Education: B.S., Microelectronics, Peking University (2009) M.S./Ph.D., Electrical Engineering, Stanford University (2011/2013) Research Themes: Emerging non-volatile memories for AI Monolithic 3D integration Energy-efficient computing systems His work spans device fabrication, circuit design, and system-level co-optimization. Recent projects are funded by NSF, DARPA, DOE, and industry partners (TSMC, Intel, Samsung), totaling >$17M. His lab, located at the Pettit Microelectronics Research Center, develops prototypes with cleanroom access. Awards: IEEE Fellow (2024) ACM/IEEE DAC Under-40 Innovators Award (2020) NSF CAREER Award (2016) Multiple editorship roles and distinguished lecturer appointments (IEEE EDS/CASS) Grants & Funding: Lead of two SRC/DARPA JUMP 2.0 centers Total research funding exceeds $17M

• Computer Architecture
• VLSI Design
• Machine Learning Acceleration
• +4 more

T. N. Vijaykumar is a Professor of Electrical and Computer Engineering at Purdue University's Elmore Family School of Electrical and Computer Engineering. His research focuses on computer architecture, VLSI design, and hardware acceleration for machine learning and datacenter systems. He holds a B.E. (Hons) in Electrical and Electronics Engineering and M.Sc.(Tech) in Computer Science from Birla Institute of Technology and Science, followed by M.S. and Ph.D. in Computer Science from the University of Wisconsin. His work spans GPU architecture optimization, memory systems, network security, and energy-efficient computing. Notable contributions include sparse tensor accelerators, disaggregated datacenter architectures, and secure speculative execution techniques. He has been actively involved in developing accelerators for machine learning inference and frameworks for distributed training of neural radiance fields. His publications address challenges in parallel computing, hardware-software co-design, and real-time systems, with applications in robotics, genomics, and microfluidics. He leads research initiatives funded by NSF and industry partnerships, emphasizing cross-layer optimizations across hardware, software, and networking layers.

• CMOS integrated circuits
• Computer architecture
• Electrical and electronic engineering
• +12 more

Maurizio Zamboni is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he also serves as Student Ombudsman. His academic career spans over three decades with continuous teaching and research contributions in electronics and computing fields. Professor Zamboni's research interests focus on cutting-edge areas including CMOS integrated circuits, computer architecture, quantum computing, semiconductor devices, and VLSI design. His work particularly emphasizes emerging nanotechnologies for digital microelectronic architectures and the design of high-performance or low-consumption processing systems. He has developed expertise in circuit architectures for probabilistic computing, logic-in-memory computing, magnetic devices, and quantum architectures. His recent publications (2021-2025) reveal a strong trend toward quantum computing applications, in-memory processing architectures, and novel approaches to overcoming the memory wall problem. These works span both theoretical algorithm development and practical hardware implementations, with significant focus on quantum annealing, FPGA-based quantum emulation, and memory-mapped processing architectures. Professor Zamboni has been actively supervising PhD students working on quantum computing algorithms, hardware AI accelerators for automotive applications, and quantum-related optimization approaches. He leads research within the VLSILAB Group at DET, focusing on the intersection of nanoelectronics, quantum computing, and advanced computer architectures. His work bridges theoretical computer science with practical electronic design, creating novel solutions for next-generation computing challenges.

Subramanian IyerView profile

Professor

• System Scaling Technology
• Advanced Packaging
• 3D Integration
• +2 more

Subramanian Iyer is a Distinguished Professor at the University of California, Los Angeles (UCLA), holding the Charles P. Reames Endowed Chair in Electrical Engineering with joint appointments in Electrical and Computer Engineering and Materials Science and Engineering. His laboratory focuses on cutting-edge semiconductor research. Primary research domains include: System Scaling Technology : Innovations in semiconductor miniaturization 3D Integration & Advanced Packaging : Techniques for vertical chip stacking and heterogeneous integration Memory Subsystems : Development of embedded DRAM and novel memory architectures Neuromorphic Computing : Hardware implementations of brain-inspired computing Publication analysis reveals three dominant themes across 35+ years of research: Semiconductor materials innovation (SiGe alloys, silicides, MBE growth) Memory technology evolution (embedded DRAM, eFUSE, low-latency designs) System integration advancements (3D packaging, TSV, heterogeneous integration) Significant honors include: IEEE Fellow (1995) and Daniel Noble Award (2012) National Academy of Inventors Fellow (2017) IBM Fellow (2010) with 30+ invention plateaus IMAPS Educator Award (2021) and Daniel C. Hughes Memorial Award (2020) He leads UCLA's NanoLab facility and has been featured in The New York Times and Wall Street Journal for pioneering chiplet technology. Current work focuses on megachip architectures and open-access semiconductor prototyping.