Sung-Kyu Lim is a Professor and the Motorola Solutions Foundation Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, where he serves as director of the GTCAD Laboratory. His educational background includes: B.S. in Computer Science from the University of California, Los Angeles (UCLA) in 1994 M.S. in Computer Science from UCLA in 1997 Ph.D. in Computer Science from UCLA in 2000 Professor Lim's research focuses on advancing VLSI design automation through physical design methodologies, 3D circuit integration, quantum circuit layout, micro-architecture exploration, and reconfigurable circuit optimization. His work bridges theoretical graph theory with practical electronic design automation challenges to improve circuit performance and scalability. His notable scientific distinctions include: NSF CAREER Award (2006) Advisory Board Member of ACM SIGDA (since 2003) Technical Program Committee roles for ICCD, ISPD, ISCAS, ASPDAC, and GLSVLSI conferences He leads the GTCAD Laboratory at Georgia Tech, driving innovation in computer-aided design tools for next-generation integrated circuits and systems.
Edoardo Charbon is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Engineering, where he leads the Advanced Quantum Architecture Lab (AQUA). He also serves on the School Council STI and is Co-Director of STI-SSIQ Administration. Previously, he was a full professor and chair at Delft University of Technology from 2008 to 2016. Charbon received his Elektrotechnik Diploma from ETH Zurich, M.S. from UC San Diego, and Ph.D. from UC Berkeley, all in electrical engineering. His career spans industry experience at Cadence Design Systems and Canesta Inc. before joining EPFL in 2002. His research focuses on ultra high-speed and 3D optical sensors, with applications in LiDAR, FLIM (Fluorescence Lifetime Imaging Microscopy), PET (Positron Emission Tomography), FCS (Fluorescence Correlation Spectroscopy), and NIROT (Near-Infrared Optical Tomography). He has pioneered deep-submicron CMOS SPAD technology, which is now mass-produced and used in smartphones, telemeters, and medical diagnostics. His recent work bridges cryo-CMOS circuits for quantum computing with advanced optical sensing techniques. Analysis of his recent publications reveals a strong trend toward integrating quantum technologies with practical imaging applications. His work spans from fundamental device development (SPAD sensors, cryo-CMOS circuits) to applied systems (LiDAR engines, medical imaging devices), with increasing integration of machine learning techniques for real-time processing. 2023 IISS Pioneering Achievement Award Fellow of the IEEE Distinguished visiting scholar, W. M. Keck Institute for Space at Caltech Fellow, Kavli Institute of Nanoscience Delft Distinguished lecturer, IEEE Photonics Society Professor Charbon has authored or co-authored over 500 papers and two books, and holds 27 patents. His research has been supported by collaborations with organizations including Bosch, X-Fab, Texas Instruments, Maxim, Sony, Agilent, and the Carlyle Group. He has driven significant innovation in CMOS SPAD technology, which is now commercially deployed in various applications. He leads the Advanced Quantum Architecture Lab (AQUA) at EPFL, which focuses on the development of advanced sensor systems combining quantum technologies with conventional electronics. The lab has been instrumental in creating SPAD-based imaging systems that push the boundaries of time-resolved optical detection.
Professor Bharat Bhuva is a faculty member in the School of Engineering at Vanderbilt University, holding the position of Professor of Electrical Engineering and Computer Engineering . His research focuses on radiation effects on integrated circuits, semiconductor device modeling, and VLSI design, with an emphasis on advancing the resilience of nanoscale electronics against single-event effects and total-ionizing-dose damage. He also investigates emerging technologies like FinFET and FDSOI for improved radiation hardness and performance. Education: Ph.D. in Electrical Engineering, North Carolina State University M.S. in Electrical Engineering, North Carolina State University B.S. in Electrical Engineering, Maharaja Sayajirao University Research Interests: Professor Bhuva’s work spans computer-aided design tools, semiconductor process modeling, and the mitigation of radiation-induced failures in advanced integrated circuits. His studies address challenges posed by scaling to smaller technology nodes (e.g., 3-nm FinFET) and the impact of environmental factors like temperature, bias conditions, and neutron exposure on circuit reliability. Key areas include multicell upsets, single-event upset (SEU) cross-section analysis, and the efficacy of radiation-hardened-by-design (RHBD) techniques. Awards & Recognition: None explicitly listed in the provided text. However, his extensive publications in top-tier journals like IEEE Transactions on Nuclear Science highlight his contributions to the field. Grants & Advising: Advises on projects related to advanced semiconductor technologies and radiation effects. His research has been supported by grants from institutions focusing on space electronics and nanotechnology. No specific grant details or student advisees are listed. Labs & Teams: Likely affiliated with Vanderbilt’s Cyber-physical Systems and Nano Science and Technology research neighborhoods, though specific lab names are not mentioned in the text.
Martin D F Wong serves as the Edward C. Jordan Professor of Electrical and Computer Engineering and Executive Associate Dean for the College of Engineering at the University of Illinois at Urbana-Champaign. He is affiliated with the Coordinated Science Laboratory and has been instrumental in advancing electronic design automation research. His educational background includes: B.Sc. in Mathematics, University of Toronto (1979) MS in Mathematics, University of Illinois at Urbana-Champaign (1981) Ph.D. in Computer Science, University of Illinois at Urbana-Champaign (1987) Wong's research centers on combinatorial optimization and algorithm design for VLSI systems, with particular expertise in lithography-aware physical design, field-programmable systems, and electronic packaging. His work bridges theoretical algorithms with practical semiconductor manufacturing challenges as feature sizes shrink below 20 nanometers. Current research focuses on integrating chip design with next-generation lithography technologies including triple-patterning, self-aligned double patterning, directed self-assembly, and extreme ultraviolet processes. His publication record shows consistent contributions to electronic design automation, with emphasis on manufacturing-aware physical design algorithms and circuit optimization techniques. Recent work addresses the critical interface between circuit layout and lithography processes as semiconductor technology advances to 14nm and beyond. Scientific recognition includes: Fellow of IEEE and ACM 2000 IEEE Donald O. Peterson Best Paper Award Multiple Best Paper Awards at DAC, ICCD, and ICCAD conferences IBM Faculty Awards (2000, 2004) NSF Research Initiation Award Wong has secured significant research funding including a $450,000 NSF grant for lithography-aware physical design and has supervised over 49 PhD students. His work continues the legacy of integrated circuit innovation at Illinois, building on foundational contributions like Jack Kilby's integrated circuit invention. Current research initiatives focus on optimizing chip design for next-generation manufacturing processes where optical interference challenges require co-design of layout and fabrication. He leads research within the Coordinated Science Laboratory, focusing on electronic design automation algorithms that address the growing complexity of semiconductor manufacturing at nanometer scales.
Zhuo Feng is Professor of Electrical and Computer Engineering at Stevens Institute of Technology, directing the HUDSON Lab and holding a Ph.D. from Texas A&M University. His research develops spectral graph methods for VLSI design, including circuit simulation, power grid verification, and machine learning applications. Funded by NSF CAREER and multiple grants, his work has produced award-winning algorithms like GRASS for graph sparsification. Recent publications focus on spectral methods for circuit stability analysis, physics-informed neural networks, and explainable AI frameworks. He teaches graduate courses in VLSI design and GPU programming while co-founding LeapLinear Solutions. NSF CAREER Award (2014) ACM/IEEE DAC Best Paper Award (2013) Multiple Best Paper Nominations (ICCAD 2008, 2006)
Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.
Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.
Abdulkadir C. Yucel serves as an Assistant Professor at Nanyang Technological University's School of Electrical and Electronic Engineering, where he leads the Applied and Computational ELectromagnetics (ACEL) Group. His research spans applied electromagnetics, radar imaging, and AI-driven electromagnetic analysis with applications in smart cities, neurotechnology, and quantum systems. Education: Ph.D. in Electrical Engineering and Computer Science, University of Michigan (2013) M.S. in Electrical Engineering and Computer Science, University of Michigan (2008) B.S. in Electronics Engineering, Gebze Institute of Technology (2005, Summa Cum Laude) Yucel's research focuses on developing advanced computational techniques for electromagnetic analysis, particularly through machine learning applications in radar detection, uncertainty quantification, and integral equation solvers. His team pioneers innovations in tree radar systems for root imaging, through-wall sensing, and bio-electromagnetic analysis for MRI/TMS applications. Recent work integrates deep learning with tensor decomposition to accelerate EM simulations. Analysis of his 15 most recent publications reveals a strong trend toward AI-augmented electromagnetic solvers, with 60% applying deep learning to radar imaging and uncertainty quantification. Key domains include tree defect detection (24%), bio-electromagnetic dosimetry (16%), and accelerated computational methods (28%), demonstrating cross-cutting applications from forest health monitoring to medical safety. Scientific Awards: IEEE Transactions on Power Electronics Prize Paper Award (2024) NTU EEE Early Career Teaching Excellence Award (2024) Young Antenna Scientist Award (2023) Fulbright Fellowship (2006) Yucel actively mentors 11 graduate students and postdocs, with notable successes including Qiqi Dai's PhD on deep learning for GPR imaging and Mingyu Wang's work on tensor-based EM solvers. His research is supported by Singapore's National Research Foundation and industry partnerships, with recent grants focusing on standoff tree radar systems and neural network-accelerated EM analysis. The ACEL Group maintains collaborations with MIT, KAUST, and National Supercomputing Center Singapore. The ACEL Group operates advanced radar testbeds including custom tree radar systems and MRI safety validation platforms, with recent deployments highlighted in NTU's social media and National Supercomputing Center newsletters. Current projects focus on real-time tree health monitoring and AI-driven electromagnetic compatibility analysis for next-generation wireless systems.
Nicola Nicolici is a Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on methods and algorithms for the design of digital integrated circuits and systems, with significant contributions in manufacturing test, post-silicon validation and debug. His work has expanded to include embedded systems, low-energy computing, and custom hardware-accelerated computing systems. Professor Nicolici's research interests span multiple areas of digital system design and validation. His early work focused on manufacturing test methodologies and power-aware testing strategies for integrated circuits. More recently, he has made significant contributions to post-silicon validation techniques, including constrained-random stimuli generation, trace signal selection, and bit-flip detection. His research has evolved to address emerging challenges in embedded computing systems, low-energy design, and specialized hardware acceleration for various applications including deep neural networks and signal processing. His recent publications reveal a strong trend toward hardware acceleration for specialized computing tasks. The research spans matrix multiplication algorithms (Strassen and Karatsuba), memory system optimization (DDR5 calibration), FPGA-based radar processing, and neural network acceleration. His work consistently bridges theoretical algorithm development with practical hardware implementation considerations, particularly focusing on precision analysis, fault tolerance, and energy efficiency. The research demonstrates a clear progression from traditional digital circuit testing to more complex system-level validation and acceleration techniques. Professor Nicolici has been actively involved in teaching courses related to system-on-chip design and test, digital systems, and embedded systems. His teaching portfolio includes advanced courses such as System-on-Chip (SOC) Design and Test and Digital Systems Design , reflecting his expertise in the field. While specific grant information isn't detailed in the provided text, his extensive publication record suggests ongoing research funding support. His research has contributed significantly to the fields of digital circuit testing, post-silicon validation, and hardware acceleration. The work has practical applications in semiconductor manufacturing, embedded systems design, and specialized computing architectures. His recent focus on neural network acceleration and memory system optimization reflects the evolving landscape of computer architecture research.
Wenjing Rao is an Associate Professor at the Department of Electrical and Computer Engineering, College of Engineering, University of Illinois at Chicago (UIC). Her research focuses on VLSI test, fault-tolerance, reliability, and hardware security in emerging nanoelectronic systems. Education: Ph.D. in Computer Science from University of California, San Diego (2008) B.S. in Computer Science from Peking University (2001) Her work explores novel computation paradigms through physical unclonable functions (PUFs), defect-tolerant logic implementation, and scalable fault tolerance in many-processor arrays. Publications emphasize hardware security, reconfiguration strategies, and reliability challenges in nanoscale architectures. Notable honors include the 2017 Harold A. Simon Award for Excellence in Teaching and the 2012 NSF CAREER Award. She has contributed to key journals like IEEE Transactions on Computer-Aided Design and conferences including DATE, ASPDAC, and NANOARCH.
David Zhigang Pan is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He also holds the Silicon Laboratories Endowed Chair. Prior to joining UT Austin, he was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His academic journey began with a B.S. from Peking University, followed by M.S. and Ph.D. degrees from UCLA. Research Areas: Electronic Design Automation (EDA), Machine Learning Hardware, FPGA Prototyping, Optical Computing, Hardware Security, and CAD for Emerging Technologies Academic Timeline: Assistant Professor (2003-2008), Associate Professor (2008-2013), Full Professor (2013-present) His research focuses on design automation for mixed-signal circuits , GPU-accelerated EDA tools , and hardware-software co-design for AI . Recent work explores FFT-based optical neural networks and deobfuscation techniques for integrated circuits , reflecting his interdisciplinary approach at the intersection of machine learning , computer architecture , and semiconductor manufacturing . Key publication trends reveal expertise in: VLSI design , lithography optimization , and deep learning applications for EDA tools. His work has been recognized with multiple Best Paper Awards at top conferences including DAC , ASP-DAC , and HOST . Awards: IEEE Fellow (2014), SPIE Fellow (2017), ACM SRC Graduate Category Honors for students Patents: 8 U.S. Patents in electronic design and hardware optimization Prof. Pan has mentored 40 PhDs and postdocs who now hold key positions in academia and industry. He leads research initiatives involving GPU acceleration frameworks and optical computing architectures . His lab focuses on vertical integration of architecture, CAD tools, and fabrication technologies for next-generation hardware solutions.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Dr. Esam Abdel-Raheem is a Professor in the Department of Electrical and Computer Engineering at the University of Windsor, Faculty of Engineering. His research focuses on digital signal processing, biomedical engineering, cognitive radio networks, and VLSI design. He holds a Ph.D. from the University of Victoria (1995) and is a Professional Engineer (P.Eng.) in Ontario and a Senior Member of IEEE. Education: B.Sc. Electrical Engineering, Ain Shams University (1984) M.Sc. Electrical Engineering, Ain Shams University (1989) Ph.D. Electrical Engineering, University of Victoria (1995) Research Interests: Dr. Abdel-Raheem’s work spans signal processing for communications, biomedical signal processing, and VLSI implementations. He has pioneered algorithms for cognitive radio networks and adaptive filtering. His recent studies leverage deep learning for medical diagnostics (e.g., lung nodule detection, Parkinson’s disease voice analysis) and cognitive radio spectrum sensing. Publications Trends: Recent work emphasizes biomedical applications (e.g., CT scan analysis, diabetic retinopathy detection) and machine learning integration in communications (e.g., federated learning for traffic crowdsourcing). His articles often bridge theoretical signal processing with practical implementations in hardware (e.g., FPGA-based filters). Awards/Grants: Not explicitly listed in the text, though his senior IEEE membership and prolific publications suggest sustained professional recognition. Lab/Teams: While not detailed, his research themes imply involvement in interdisciplinary teams focusing on biomedical engineering, telecommunications, and VLSI design.
Professor Serdar Özoğuz is a full faculty member at the Department of Electronics and Communication Engineering , Istanbul Technical University . Holding a Ph.D. from ITU (2000) and a M.Sc. from ITU (1993) , he has taught courses like Active Network Synthesis , Basics of Electrical Circuits , and Scientific Research Ethics since 2014. His research focuses on Active RC filters Nonlinear electronic circuits Analog integrated circuit design Network synthesis . His recent publications emphasize machine learning applications in RF/microwave design , quantum computing for CAD tools , and emerging memory devices . The department's Devreler ve Sistemler Laboratuvarı Çok Geniş Ölçekli Tümdevre (VLSI) Tasarımı Laboratuvarı likely support his work. Despite no explicit awards listed, his 15+ recent articles in high-impact journals underscore his technical contributions.
Giovanni De Micheli is a Professor of Electrical Engineering and Computer Science at EPF Lausanne, Switzerland. He also serves as Director of the Integrated Systems Centre and the Institute of Electrical Engineering at EPFL, and chairs the Scientific Committee of CSEM in Neuchatel. Previously, he held academic roles at Stanford University for 18 years, including Full Professor, Associate Professor, and Assistant Professor in the Department of Electrical Engineering. His research spans synthesis of digital circuits, hardware/software co-design, low-power design, and Networks on Chip (NoC) technology. 2003: IEEE Emanuel Piore Award 2000: Golden Jubilee Medal of the IEEE CAS Society 2000: ACM Fellow 1994: IEEE Fellow 1990: IEEE/CS Distinguished Service Award 1988: NSF Presidential Young Investigator Award His seminal contributions include pioneering C-based synthesis and Boolean matching algorithms for digital circuits, foundational work in dynamic power management using stochastic control, and the development of Network-on-Chip (NoC) technology. His publications, such as "Networks on Chips: A New SoC Paradigm" and "Dynamic Power Management for Portable Systems" , have shaped modern SoC design practices. With over 400 technical articles, 9 books, and an H-index of 56, his work remains highly influential.
