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Giovanni De MicheliView profile

Professor

• Integrated Circuit Design
• Hardware Synthesis
• Logic Optimization
• +5 more

Giovanni De Micheli is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL), holding appointments in both the School of Computer and Communication Sciences (IC) and the School of Engineering (STI). He is affiliated with the Integrated Systems Laboratory (LSI) and serves as Scientific Director of EcoCloud. His primary office is located in INF 341 building at EPFL's Lausanne campus where he conducts research and teaching activities. Professor De Micheli's research spans multiple domains in electronic design automation and integrated circuit design. His primary interests include: Integrated Circuit Design and Hardware Synthesis Logic Optimization and Boolean Methods Nanoelectronics and 2D Electronics Quantum Computing and Emerging Technologies Low-Power Electronics and Energy-Efficient Systems Electronic Design Automation for Novel Computing Paradigms His recent publications demonstrate a strong focus on advancing logic synthesis techniques for both conventional and emerging technologies. Professor De Micheli's work bridges theoretical foundations with practical applications, particularly in adapting traditional EDA methods to novel computing paradigms like quantum computing and superconducting electronics. His research group has made significant contributions to the development of efficient algorithms for circuit optimization across multiple technology domains, with particular emphasis on area, power, and delay optimization while maintaining functional correctness. Professor De Micheli has supervised numerous doctoral students throughout his career at EPFL, mentoring over 40 PhD candidates whose research spans various aspects of electronic design automation, circuit design, and emerging technologies. His students have gone on to make significant contributions in both academia and industry. As Scientific Director of EcoCloud, Professor De Micheli leads research initiatives focused on energy-efficient computing systems and sustainable cloud infrastructure. His laboratory, the Integrated Systems Laboratory, serves as a hub for interdisciplinary research connecting computer science, electrical engineering, and materials science, with particular focus on next-generation computing technologies.

Subhasish MitraView profile

Professor

• Robust Computing
• NanoSystems
• Electronic Design Automation (EDA)
• +3 more

Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.

H.-S. Philip WongView profile

Professor

• Nanotechnology
• Semiconductor Technology
• Solid-State Devices
• +5 more

H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University, where he has been since 2004. He holds the rank of Professor in the Department of Electrical Engineering and serves as the Director of the Stanford Nanofabrication Facility. Prior to Stanford, he spent 16 years at IBM’s T.J. Watson Research Center and served as Vice President of Corporate Research at TSMC (2018–2020), remaining as Chief Scientist in an advisory role thereafter. Leadership roles include founding the Stanford SystemX Alliance and leading the Microelectronics Commons AI Hardware Hub funded by the CHIPS Act. Research focuses on nanotechnology, semiconductor devices, and next-generation computing architectures, including carbon nanotube electronics, 3D integration (N3XT/MOSAIC), and neuromorphic computing. Awarded IEEE Fellow (2001), the IEEE Andrew S. Grove Award, and the J.J. Ebers Award for contributions to electron devices. His work spans device physics, fabrication, and system integration, with over 600 publications. Key contributions include advancements in phase-change memory, carbon nanotube transistors, and compute-in-memory systems. He advises numerous students and collaborates with industry through initiatives like the Stanford Non-Volatile Memory Technology Research Initiative. Recent efforts emphasize AI hardware acceleration, cryo-CMOS for quantum computing, and scalable memory architectures. His lab innovations include CellChips for synthetic biology and hyperdimensional computing using 3D RRAM.

Baker MohammadView profile

Professor

• Very-Large-Scale Integration (VLSI)
• Hardware Accelerators for Artificial Intelligence
• Hardware Security
• +7 more

Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.

Suman DattaView profile

Professor

• Semiconductor Devices
• Nanotechnology
• VLSI Systems
• +7 more

Suman Datta is a Professor at the Georgia Institute of Technology , holding the Joseph M. Pettit Chair in Advanced Computing and Georgia Research Alliance Eminent Scholar titles. He has a joint appointment with the School of Materials Science and Engineering. Education : B.Tech in Electrical Engineering from IIT Kanpur; Ph.D. in Electrical and Computer Engineering from the University of Cincinnati. Prior Appointments : Stinson Endowed Chair Professor of Nanotechnology at University of Notre Dame (2015–2022); Professor at Penn State (2007–2015); Intel Corporation (1999–2007) in Advanced Transistor Group. Research Interests : His work focuses on high-performance heterogeneous computing using advanced CMOS and beyond-CMOS semiconductors. Key areas include ferroelectric field-effect transistors (FeFETs) , cryogenic computing , in-memory computing , and brain-inspired computing . He explores materials like ferroelectric gate stacks , insulator-to-metal phase transition oxides , and high-mobility oxides for next-generation compute architectures. Recent Article Trends : His group’s publications emphasize BEOL-compatible oxide transistors , negative capacitance , radiation-resilient devices , and machine learning-aided modeling . Subfields include low-voltage memory , 3D Ising machines , dynamic logic at cryogenic temperatures , and monolithic integration of power delivery systems. Scientific Awards : IEEE Fellow (2013) for contributions to transistor technologies NAI Fellow (2016) for societal impact via patents Intel Achievement Award (2003) for high-k/metal gate CMOS Intel Logic Technology Quality Award (2002) for Tri-gate transistors SEMI Award (2012) for high-k dielectrics Penn State Outstanding/ Premier Research Awards (2012, 2015) Advising & Grants : He has mentored students like Wriddhi Chakraborty , Khandker Akif Aabrar , and Sourav Dutta . His research is funded by SRC , DARPA , and NSF , including leadership of the ASCENT and EXCEL centers. Labs & Collaborations : Datta directs the STAR Lab at Georgia Tech, which specializes in atomistic modeling , nanofabrication , and compact model development . The lab collaborates with industry giants like Intel , Micron , and IBM through the ASCENT center.

Qing CaoView profile

Associate Professor

• Nanomaterials
• Electronic Devices
• Optoelectronic Devices
• +5 more

Qing Cao is an Associate Professor of Materials Science and Engineering at the University of Illinois at Urbana-Champaign, with courtesy appointments in Chemistry and Electrical Engineering. He leads the Cao Research Group within the Grainger College of Engineering and serves as Deputy Editor of Science Advances. Dr. Cao received his B.S. in Chemistry from Nanjing University in 2004 and his Ph.D. in Materials Chemistry from the University of Illinois at Urbana-Champaign in 2009. After working for 9 years as a research scientist at IBM Thomas J. Watson Research Center, he returned to UIUC in 2018 as a faculty member. His research focuses on developing functional nanomaterials for unconventional electronic systems, high-performance logic devices, and low-cost energy harvesting. The Cao Research Group specifically works on: nanoelectronic devices based on novel nanomaterials; next-generation memory devices for neuromorphic and in-memory computing; monolithic 3D integration for high performance electronics; high-performance printable electronic materials; and bioelectronics for healthcare applications. His work bridges materials science, chemistry, electrical engineering, and device physics. Analysis of Dr. Cao's recent publications reveals a strong focus on electrochemical memory devices for neuromorphic computing, with significant work on carbon nanotube-based electronics and novel nanomaterials. His 2023 Nature Electronics paper on CMOS-compatible electrochemical synaptic transistors demonstrates his leadership in developing hardware solutions for deep learning acceleration. His research trajectory shows a progression from fundamental carbon nanotube device physics to more applied systems for computing and sensing applications. IBM Pat Goldberg Memorial Best Paper Award (2017) IBM Master Inventor Award (2016) MIT Technology Review TR35 (2016) Forbes '30 Under 30' (2012) and 'Most Influential All-Star Alumni' (2016) Atlantic Council Millennium Fellow (2017) US Frontiers of Engineering by National Academy of Engineering (2016, 2019) 17 IBM Invention Achievement Awards (2011-2018) Dr. Cao has secured significant research funding including NSF grants 1950182 and 2139185. His research group actively recruits graduate students and postdoctoral researchers to work on cutting-edge materials and device projects. His work has resulted in over thirty research papers and fifty patents and patent applications. He teaches graduate courses including MSE 403 (Synthesis of Materials), MSE 460 (Electronic Materials I), and MSE 488 (Optical Materials). The Cao Research Group operates within the University of Illinois' world-class facilities including the Frederick Seitz Materials Research Laboratory and Holonyak Micro and Nanotechnology Laboratory. His research has received support from NSF, DoD, DOE, and industry partners including TSMC. The group's recent $2 million project focuses on developing technology to help mobile devices learn and adapt to their surroundings.

Aaron TheanView profile

Professor

• Semiconductor Technology
• Advanced Electronics
• Nanoelectronics
• +6 more

Prof Aaron Thean is the Deputy President (Academic Affairs) and Provost at the National University of Singapore (NUS). Formerly, he served as Dean of the College of Design and Engineering at NUS and held senior roles at IMEC (Belgium) as Vice President of Logic Technologies and Director of Logic Devices Research. His expertise spans advanced semiconductor device technologies, including FinFETs, nanowire FETs, III-V/Ge channels, and emerging beyond-CMOS architectures. He holds degrees from the University of Illinois Urbana-Champaign (B.Sc., M.Sc., Ph.D. in Electrical Engineering) and has published over 300 papers with 50+ patents. His awards include the Gregory Stillman Award (2001) and Compound Semiconductor Innovation Award (2014). Research interests focus on semiconductor innovation, device-process co-optimization (DTCO), and monolithic 3D integration. Notable contributions include industry-first Gate-First HKMG technologies, advanced strained silicon platforms, and neuromorphic computing hardware. His work bridges academia and industry through collaborations with Qualcomm, IBM, and foundry partners. Current initiatives emphasize energy-efficient computing and wearable sensor systems. Prof Thean’s leadership spans NUS-wide academic strategy and global research partnerships. His technical legacy includes foundational advancements in transistor scaling, low-power CMOS design, and AI-driven failure analysis methodologies.

Azad J NaeemiView profile

Professor

• Nanotechnology
• Nanoelectronics
• Spintronics
• +5 more

Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.

Kyojin ChooView profile

Assistant Professor

• Charge-domain circuits
• Sensor interfaces
• Energy converters
• +4 more

Kyojin Choo is a Tenure Track Assistant Professor at the Swiss Federal Institute of Technology Lausanne (EPFL) in the School of Engineering , affiliated with the Mixed-Signal Integrated Circuits Lab (MSIC-LAB). He also holds teaching roles in Microengineering and Electrical and Electronics Engineering at EPFL. B.S. and M.S. in Electrical Engineering from Seoul National University (2007, 2009) Ph.D. in Electrical Engineering from the University of Michigan (2018) His research focuses on charge-domain analog/mixed-signal circuits , low-power sensor interfaces , and compact ADCs for IoT, wearables, and millimeter-scale systems. He has pioneered charge-injection cell techniques for energy-efficient circuits in energy management, sensor front-ends, and communication. His work emphasizes reducing power consumption to nanowatt levels while enabling ultra-compact designs. His recent publications highlight advancements in compact SAR ADCs , low-power MEMS accelerometers , millimeter-scale imaging systems , and ultra-low-power timing generators . His research integrates charge-domain circuit design with sensor interface optimization , energy harvesting , and high-speed link architectures . He holds over 20 US patents and has taught courses in Microengineering and Electrical Engineering at EPFL. His group (MSIC-LAB) addresses challenges in battery-free sensor design, power-constrained system scaling, and commercialization of wearables with unconventional form factors.

• Neuromorphic Computing
• Memristor-Based Architectures
• Energy-Efficient AI Hardware
• +7 more

Said Hamdioui serves as a full Professor in the Department of Computer Engineering within the Faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology. His research focuses on cutting-edge hardware architectures for neuromorphic computing and energy-efficient AI acceleration, with particular emphasis on memristor-based systems, emerging memory technologies, and fault-tolerant designs for edge applications. His research interests span Neuromorphic Computing , Memristor-Based Architectures , and Energy-Efficient AI Hardware , addressing critical challenges in hardware security, computation-in-memory, and reliable edge AI deployment. Recent work demonstrates significant advancements in RRAM/FeFET testing methodologies, spiking neural network implementations, and spin wave computing alternatives to traditional CMOS. His publications reveal strong trends toward real-world deployment of brain-inspired hardware with practical constraints like power efficiency, testability, and security. Award highlights include: DATE'20 Best Paper Award DFT'21 Outstanding Student Paper ETS 2021 Best Paper Award LATS 2018 & 2022 Best Paper Awards Professor Hamdioui actively contributes to the research community through editorial roles at IEEE Transactions on VLSI Systems , IEEE Design & Test , and Journal of Electronic Testing from 2017-2018. His leadership in multi-partner projects like CONVOLVE and NEUROKIT2E demonstrates strong industry-academia collaboration for edge AI solutions. Current work shows increasing focus on practical deployment challenges including in-field fault monitoring, security vulnerabilities in neuromorphic systems, and realistic brain simulation frameworks.

Joseph FriedmanView profile

Associate Professor

• Artificial Intelligence Hardware
• Beyond-CMOS Computing
• Neuromorphic Computing
• +6 more

Joseph S. Friedman is an Associate Professor of Electrical & Computer Engineering at the University of Texas at Dallas, leading the NeuroSpinCompute Laboratory within the Erik Jonsson School of Engineering and Computer Science. His research focuses on unconventional computing paradigms leveraging nanotechnology, including neuromorphic systems, spintronics, and memristive devices. He specializes in nanomagnet-based logic architectures, neuromorphic computing with domain walls and skyrmions, and hardware security for emerging technologies. His research explores energy-efficient computing through novel paradigms such as reversible skyrmion logic, neuromorphic networks using magnetic tunnel junctions, and stochastic Bayesian inference circuits. He has pioneered spintronic neurons demonstrating 94% accuracy in handwritten digit recognition and developed secure logic locking mechanisms using nanomagnet logic. His work integrates experimental fabrication with SPICE modeling, emphasizing scalable beyond-CMOS systems. Recent advancements include toggle SOT-MRAM architectures, quantum circuit design for neutral atom systems, and neuromorphic networks leveraging superconducting flux quanta. He advises over 20 graduate and undergraduate students, fostering innovation in AI hardware and unconventional computing. Notable projects include the NeuroSpinCompute Lab's domain wall neuromorphic networks, secure logic locking schemes, and collaborations with institutions like Sandia National Labs on neuromorphic reservoir computing. Current research trends emphasize low-energy spintronic architectures, hybrid quantum-classical systems, and neuromorphic applications in edge computing. His research is supported by NSF grants CCF-1910800 and CCF-2146439, focusing on neuromorphic and spintronic systems. He regularly contributes to conferences like IEEE Rebooting Computing and SPIE Spintronics, showcasing breakthroughs in nanomagnetic logic and neuromorphic inference.

Tathagata SrimaniView profile

Assistant Professor

• Nanotechnology
• Beyond-silicon CMOS technologies
• 3D Integration
• +7 more

Tathagata Srimani is an Assistant Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University (CMU), affiliated with the College of Engineering. He previously served as a Postdoctoral Scholar in Electrical Engineering at Stanford University. His academic journey includes a Ph.D. and S.M. in EECS from MIT (2022 and 2018 respectively) and a B.Tech. in E&ECE from IIT Kharagpur (2016). Research Focus: Srimani’s work centers on nanoelectronics and transformative NanoSystems. Key areas include: Carbon nanotube field-effect transistors (CNFETs) and their monolithic 3D integration with silicon Ultra-dense 3D integration of logic and memory to address the 'memory wall' in AI/ML Technology-architecture co-design frameworks for energy-efficient computing Key Achievements: Developed first silicon fab-compatible CNFET processes (TNANO ’18, Nature ’19) Enabled CNFET RISC-V microprocessor and monolithic 3D integration with Analog Devices/SkyWater Recipient of MIT Presidential Fellowship (2016) and Morris Joseph Levin Award (2018) Teaching & Outreach: Teaches semiconductor devices and hardware design, including hands-on 'Hacker Fab' courses. Leads the NEXUS Research Group exploring heterogeneous nanomaterials (e.g., magnetic and oxide semiconductors) and thermal/power management in 3D systems. Future Directions: Expanding into probabilistic computing hardware, co-design frameworks for application-specific systems, and scaling 3D NanoSystem technologies for industrial adoption.

Songbin GongView profile

Associate Professor

• RF and microwave photonics
• Antennas for communication and wireless sensing
• Microwave acoustics
• +7 more

Songbin Gong is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana Champaign, where he has been a faculty member since August 2013. He was promoted from Assistant Professor to Associate Professor in August 2019 and holds the Intel Alumni Fellowship. His research is centered at the Micro and Nanotechnology Lab, where he leads the Integrated RF Microsystems research group. Professor Gong's research focuses on RF and microwave photonics, microwave acoustics, and Micro-Electro-Mechanical Systems, with particular expertise in lithium niobate-based devices. His work spans the development of acoustic resonators, filters, and transducers operating from VHF to Sub-THz frequencies. Recent publications demonstrate significant advances in high-frequency acoustic devices, including GHz resonators with high electromechanical coupling and low loss characteristics. His research has direct applications in 5G communications, wireless sensing, and imaging systems. Gong has established himself as a leader in the field of RF MEMS and acoustic devices, with numerous high-impact publications in top journals including IEEE Transactions on Microwave Theory and Techniques, Journal of Microelectromechanical Systems, and Optics Express. His work shows a clear progression toward higher frequency operation, improved device performance, and novel integration approaches for next-generation communication systems. Among his notable achievements is the development of thin-film lithium niobate devices that overcome traditional frequency limitations of MEMS resonators, enabling operation beyond 10 GHz. This work addresses critical challenges in 5G and future wireless technologies where conventional approaches face scaling limitations. IEEE Ultrasonics Early Career Investigator Award DARPA Young Faculty Award 2014 NASA Early Career Faculty Award 2017 Intel Alumni Fellow 2017-present Multiple Best Paper Awards at major conferences including International Ultrasonic Symposium and International Microwave Symposium Professor Gong actively mentors graduate and undergraduate students, with several of his PhD students achieving notable success, including Ruochen Lu who joined UT Austin as a tenure-track assistant professor. His research group has secured significant funding from agencies including DARPA and NASA, supporting cutting-edge work in RF microsystems. The group maintains strong industry connections, particularly with Intel, reflecting the practical relevance of their research to commercial communication technologies. The Gong Research Group leverages micro/nano electro mechanical systems (N/MEMS), integrated photonic, and compound semiconductor technologies to develop chip-scale hybrid microsystems for RF communication, sensing, and imaging applications. Their current work focuses on pushing the boundaries of acoustic device performance while maintaining compatibility with standard semiconductor manufacturing processes.

Erica R.H. FuchsView profile

Professor

• Technology Policy
• Global Manufacturing
• Innovation Policy
• +3 more

Erica R.H. Fuchs is the Kavčić-Moura Professor in the Department of Engineering and Public Policy at Carnegie Mellon University (CMU), directing the Critical Technology Initiative (CTI). She holds courtesy faculty positions in Materials Science and Engineering and the Heinz College. Her research focuses on emerging technology development, commercialization, and global manufacturing, with emphasis on national policy implications. Fuchs leads interdisciplinary efforts at CTI to advance critical technology assessment frameworks, ensuring smart investments and policies for national security and economic competitiveness. Formerly, she directed the Manufacturing Futures Initiative, now an endowed institute at CMU. Education: She earned a Ph.D. (2006), M.Sc. (2003), and B.Sc. (1999) in Engineering Systems, Technology Policy, and Materials Science from MIT. Post-MIT, she was a UNIDO fellow in Beijing. Research Interests: Global innovation policy, technology commercialization pathways, and the intersection of technology with economic and security objectives. She authored influential works like the 2021 report *Securing America’s Future*, advocating for a National Technology Strategy to align multi-objective outcomes (security, equity, prosperity). Key Contributions: Catalyzed the National Network for Critical Technology Assessment, mobilizing 13+ universities to address technology gaps. Testified in Congress on supply chain resilience, EV battery policies, and semiconductor strategies. Advises entities like the National Semiconductor Technology Center and MIT’s Institute for Data, Systems, and Society. Affiliations: National Bureau of Economic Research (Research Associate), National Institute of Standards and Technology (NSTC Board), and Brookings Institution panelist. Her work is frequently cited in *Axios*, *Bloomberg*, and the *New York Times*.

• Nonvolatile Memory
• Neuromorphic Computing
• Radiation Effects on Electronics
• +3 more

Matthew J. Marinella serves as an Associate Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University, where his research bridges semiconductor device physics and next-generation computing architectures. His work focuses on enabling reliable computing systems for extreme environments through novel memory technologies. His academic foundation includes: Ph.D. in Electrical Engineering, Arizona State University (2008) Marinella's research centers on nonvolatile memory devices (particularly ECRAM and SONOS technologies), neuromorphic computing systems, and radiation effects characterization. He pioneers analog in-memory computing solutions resilient to space radiation, with expertise spanning electrochemical memory physics, radiation-hardened circuit design, and emerging device applications for artificial intelligence. His experimental work combines nanoscale imaging with computational modeling to understand device degradation mechanisms under ionizing radiation. Analysis of his 2023-2025 publications reveals a dominant focus on radiation-tolerant neuromorphic systems, with 70% of recent work addressing radiation effects on emerging memories. Key thematic clusters include TaOx ECRAM characterization under gamma/heavy-ion exposure (25% of publications), analog in-memory computing fault tolerance (30%), and novel test platforms for memory device benchmarking (20%). This research directly enables space-based computing applications where radiation resilience is non-negotiable. As a technical leader, Marinella chairs the Emerging Memory Devices Section for the IRDS Roadmap Beyond CMOS Chapter and serves on the SRC Decadal Plan Executive Committee. His Sandia legacy includes founding the Secure, Efficient, Extreme Environment Computing (SEEEC) Grand Challenge. At ASU, he mentors graduate researchers through thesis supervision in EEE 599/799 courses and directs laboratory work on memory device characterization, though specific student names and grant awards aren't publicly enumerated. His laboratory operations emphasize radiation testing infrastructure and analog computing testbeds, supporting collaborative projects with national labs on space electronics hardening. Current efforts integrate magnetic domain wall devices with resistive memories to create hybrid neuromorphic systems capable of operating in extreme environments where conventional CMOS fails.