Naresh R. Shanbag

Naresh R. Shanbag is the Jack S. Kilby Professor of Electrical and Computer Engineering at the University of Illinois, affiliated with the Coordinated Science Lab (414). His expertise spans energy-efficient machine learning systems, communication systems in scaled silicon and beyond CMOS technologies, VLSI architectures, and integrated circuit design. He holds a Ph.D. in Electrical Engineering from the University of Minnesota, awarded in June 1993.

Dr. Shanbag has been recognized for his teaching excellence with multiple listings in the University of Illinois's 'Incomplete List of Teachers Ranked Excellent' across various academic terms: Fall 2020, 2019, 2018, 2012, and 2011. His research focuses on advancing energy and latency-efficient solutions in machine learning, communications, and signal processing, leveraging interdisciplinary innovations in systems, algorithms, and integrated circuits.

Key honors and awards include the 2024 Semiconductor Innovation Award, the 2021 Neural Information Processing Systems Spotlight Paper, and the IEEE Fellow distinction in 2006. He has also received the D. J. Gandhi Distinguished Visiting Professorship from IIT Mumbai, India, and numerous best paper awards from prominent conferences like IEEE ISCAS and ISLPED.

He actively mentors undergraduates in integrated circuit design, VLSI architectures for DSP/communications, and machine learning implementations. His research group innovates in deep in-memory architectures for edge inference, resource-constrained machine learning platforms, and VLSI circuits for autonomous systems and AI. He has authored/co-authored influential books, including 'Deep In-memory Architectures for Machine Learning' (2020) and 'Pipelined Adaptive Digital Filters' (1994).