Zhuo Feng is Professor of Electrical and Computer Engineering at Stevens Institute of Technology, directing the HUDSON Lab and holding a Ph.D. from Texas A&M University. His research develops spectral graph methods for VLSI design, including circuit simulation, power grid verification, and machine learning applications. Funded by NSF CAREER and multiple grants, his work has produced award-winning algorithms like GRASS for graph sparsification. Recent publications focus on spectral methods for circuit stability analysis, physics-informed neural networks, and explainable AI frameworks. He teaches graduate courses in VLSI design and GPU programming while co-founding LeapLinear Solutions. NSF CAREER Award (2014) ACM/IEEE DAC Best Paper Award (2013) Multiple Best Paper Nominations (ICCAD 2008, 2006)
Dr. Muhammad Rashed is an Assistant Professor in the Department of Computer Science and Engineering at the University of Texas at Arlington, within the College of Engineering. He holds a Ph.D. in Computer Engineering from the University of Central Florida (2024) and a B.S. in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology (2015). Ph.D. : Computer Engineering, University of Central Florida, 2024 B.S. : Electrical and Electronics Engineering, Bangladesh University of Engineering and Technology, 2015 His research focuses on electronic design automation (EDA), in-memory computing, AI acceleration, and sustainable computing. He explores novel computing paradigms to overcome the limitations of traditional architectures, particularly in data-intensive applications such as AI and scientific computing. His work emphasizes hardware-software co-design and leveraging emerging non-volatile memories for energy-efficient processing. The 15 most recent publications highlight a consistent focus on in-memory computing, particularly in path-based and flow-based architectures, logic synthesis, and AI acceleration. Key themes include optimization, fault tolerance, verification, and the use of advanced data structures like sentential decision diagrams. His work is published in top-tier venues such as DAC, ICCAD, ASP-DAC, and IEEE/ACM journals. Scientific Awards: UTA CARES Grant for OER Creation Research Experiences for Undergraduates (REU) Grant Alireza Seyedi Doctoral Research Innovation Endowed Scholarship David T. & Jane M. Donaldson Memorial Scholarship IEEE/ACM William J. McCalla ICCAD Best Paper Award Nomination Best Research Video Award, Design Automation Conference (DAC) Dr. Rashed advises several graduate and undergraduate students in the NextGen Computing Lab and is involved in research grants including the UTA CARES Grant and REU funding. He actively contributes to academic service through roles such as conference TPC member, journal reviewer (e.g., IEEE TCAD, ACM TODAES), and committee participation in the department and college. His lab, the NextGen Computing Lab, is dedicated to building scalable, energy-efficient computing systems for next-generation AI and scientific workloads, aligning with national initiatives in advanced computing.
Dr. Chih-Hung (James) Chen is a Professor in the Department of Electrical & Computer Engineering at McMaster University. His research focuses on noise-related issues in semiconductor devices, low-noise circuit design for medical and communication applications, and thermal noise characterization in nano-scale transistors. He holds senior member status in IEEE and is a licensed Professional Engineer in Ontario. Education: Ph.D., McMaster University, 2002 M.A.Sc., Simon Fraser University, 1997 B.Sc., National Central University, Taiwan, 1991 Research interests include biomedical technologies, microelectronics & VLSI, and digital/smart systems. He has collaborated with companies like Sony Corporation, United Microelectronics Corporation, and Focus Microwaves. His work is supported by grants from the Canada Foundation for Innovation (CFI), NSERC, and the Ontario Innovation Trust (OIT). Notable achievements include serving on the International Advisory Committee of the International Conference on Noise and Fluctuations (2015) and as an editor for the Journal of Low Power Electronics and Applications since 2022. Teaching includes courses like Analysis and Design of RF ICs for Communications and Electronic Devices and Circuits 2. His research lab focuses on advancing noise measurement techniques and designing ultra-low-power analog circuits for emerging applications.
Prof. Dr. Tobias Gemmeke is a University Professor at RWTH Aachen University's Faculty of Electrical Engineering and Information Technology, leading the Chair of Integrated Digital Systems and Circuit Design. His work focuses on neuromorphic computing, hardware accelerators, and energy-efficient electronics. He has pioneered advancements in FPGA-based computational neuroscience simulators, neuromorphic processor architectures, and sensor integration for industrial and medical applications. Research interests include time-domain computing, ReRAM reliability, and co-optimization of neural networks with hardware. Notable contributions include the neuroAIx framework for accelerated neuroscience simulations and energy-efficient ASIC designs for post-quantum cryptography. He actively explores memristive devices and domain generalization techniques for edge computing. Recent publications highlight innovations in spiking neural networks, sensor systems for plain bearings, and time-domain compute-in-memory engines. His work bridges theoretical neuroscience with practical hardware implementations, emphasizing scalability and real-time performance.
Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.
Ambrose Adegbege serves as Professor of Electrical and Computer Engineering and Coordinator for Engineering Science at The College of New Jersey (TCNJ), where he directs the Laboratory for Embedded Control and Optimization (LECO). A Professional Engineer and IEEE member, he holds leadership roles including Faculty Advisor for the National Society for Black Engineers since 2013. Education: Ph.D. in Electrical and Electronic Engineering, The University of Manchester (2011) M.Sc. in Electrical and Electronics Engineering, The University of Manchester (2006) B.Sc. in Electronic and Electrical Engineering, Obafemi Awolowo University (2004) Professor Adegbege's research centers on constrained control systems , fast optimization algorithms , and analog VLSI circuits for embedded implementations . His work bridges theoretical control theory with hardware design, focusing on real-time model predictive control (MPC) for input-constrained systems. Key innovations include analog solvers for MPC, inexact optimization methods, and anti-windup techniques that maintain stability under physical limitations. Analysis of his 15 most recent publications (2018-2026) reveals a dominant focus on hardware-accelerated MPC implementations, with 70% addressing analog/digital architectures for real-time control. His work consistently tackles computational bottlenecks through novel primal-dual dynamics (40% of publications) and constrained optimization (60%), demonstrating strong industry relevance in robotics and renewable energy systems. Scientific Awards: Fulbright Fellowship (2023) Carnegie African Diaspora Fellowship (2021) Excellence in Student Mentoring Award (2023) SOSA Award (2023) Four consecutive Engineering Research Prizes (2018-2021) Secured $432,235 in external funding including an NSF grant for ultra-fast embedded control architectures ($196,380) and a DOD instrumentation grant ($235,855). His mentoring excellence is evidenced by sustained NSBE leadership and student co-authorship on 12 publications since 2018. Current research in LECO integrates FPGA and analog VLSI to overcome computational barriers in safety-critical control systems. LECO advances embedded control through three core thrusts: analog optimization circuits, constrained primal-dual dynamics, and hardware/software co-design. Recent projects include quadruple-tank system implementations and renewable energy grid controllers developed with MIT collaborators during his Masdar Institute postdoc.
Stephen W. Keckler is an Adjunct Professor at the Department of Computer Science , The University of Texas at Austin , and serves as Vice President of Architecture Research at NVIDIA . He is an ACM Fellow , IEEE Fellow , and Sloan Foundation Research Fellow . Education: BS in Electrical Engineering, Stanford University (1990) SM in Computer Science, Massachusetts Institute of Technology (1992) PhD in Computer Science, MIT (1998) Research Interests focus on computer architecture for deep learning , GPU computing , and energy-efficient systems . His work explores memory compression , network-on-chip designs , and heterogeneous computing . Publication Trends highlight advancements in deep learning accelerators , GPU memory systems , and energy-efficient architectures . Notable themes include sparsity exploitation , multi-chip modules , and fault-tolerant GPU pipelines . Scientific Recognition : ACM Fellow IEEE Fellow Sloan Foundation Research Fellow Best Paper Awards at ASPLOS 2009 and ISPASS 2011 Laboratory Affiliations : Computer Architecture and Technology Laboratory (CART) TRIPS Project (Tera-Op Reliable Intelligently adaptive Processing System) NVIDIA Research
Günter Rote is a Professor in the Department of Computer Science at Freie Universität Berlin, specifically within the Theoretical Computer Science group (Arbeitsgruppe Theoretische Informatik). He holds a formal academic title of Professor Dr. and is affiliated with the Faculty of Mathematics and Computer Science. His research focuses on theoretical computer science, computational geometry, algorithms, and discrete mathematics. Key research interests include geometric algorithms, optimization problems (e.g., shortest paths, traveling salesman problems), and algorithm design for parallel computing systems. His work spans topics such as systolic arrays, convex hulls, and combinatorial optimization. Rote’s contributions include foundational studies on computational geometry problems, algorithmic complexity, and practical applications in energy equity and infrastructure design. Publications highlight contributions to solving extremal equations, polygon transformations, and the quadratic assignment problem. He has been active in academic leadership, mentoring students, and contributing to computational science communities. His email is rote@inf.fu-berlin.de, and his office is located at Takustraße 9 in Berlin.
Boris Murmann is Professor at Stanford University, specializing in integrated circuit design, mixed-signal computing, and energy-efficient AI hardware. His research advances neural interface technologies, analog design automation, and tinyML systems. Recent work develops ultra-low-power neural recording ICs for brain-computer interfaces, RRAM-based memory systems, and open-source semiconductor design frameworks. Publications demonstrate innovations in compressive sensing for neural data, hardware-algorithm co-design, and reinforcement learning for analog circuit synthesis. Significant contributions include Medusa (TinyML processor), EMBER (RRAM macro), and methodologies for coarsely-quantized computer vision and analog design automation.
Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She also serves as the Acting Associate Dean for Research at the Grainger College of Engineering. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a collaboration between the University of Illinois, North Carolina State University, and Penn State University. Education: Ph.D. in Electrical Engineering, University of California, Berkeley, 1992 M.S. in Electrical Engineering, Stanford University B.S. in Electrical Engineering, Cornell University (with distinction) Research Interests: Her research focuses on machine learning applications in electronics, ESD-robust high-speed I/O circuit design, compact modeling, behavioral modeling of circuits, and CDM-ESD protection for advanced packaging technologies. Scientific Awards: IEEE Fellow for contributions to electrostatic discharge reliability of integrated circuits Best Student Paper Award, IEDM Outstanding and Best Paper Awards, EOS/ESD Symposium Technical Excellence Award, SRC NSF CAREER Award IBM Faculty Award ESD Association’s Industry Pioneer Recognition Award Advising and Grants: She supervises graduate and undergraduate researchers, primarily focusing on those with strong academic records and relevant experience. Her work is supported by NSF and other prominent organizations. Labs and Teams: She leads the CAEML center, which aims to apply machine learning to optimize microelectronic circuits and systems, enhancing design automation and reliability.
Ayse Coskun is a Professor in the Electrical and Computer Engineering Department at Boston University's College of Engineering. She serves as Director of the Center for Information and Systems Engineering (CISE) and as interim Associate Dean for Research and Faculty Development. Her research focuses on the intersection of computer systems, energy efficiency, and AI. Dr. Coskun received her PhD from the University of California, San Diego in 2009. Prior to joining academia, she worked at Sun Microsystems (now Oracle). Her research spans energy-efficient computing, cloud computing, high performance computing, computer architecture, and embedded systems, with recent work focusing on AI's impact on data center energy demands. Her publication record shows consistent innovation across multiple domains, with recent work emphasizing AI applications for improving cloud security (through frameworks like DeltaSherlock and Praxi) and transforming data centers into grid-responsive assets (Emerald AI project). Her research bridges theoretical advances with practical applications, resulting in tools adopted by industry partners including IBM. IBM Faculty Award (2020) Ernest S. Kuh Early Career Award (2017) NSF CAREER Award (2012-2017) Multiple best paper and artifact awards at top conferences As an educator, Dr. Coskun teaches courses including EC327 Introduction to Software Engineering, EC535 Introduction to Embedded Systems, and EC713 Advanced Computing Systems and Architecture. She has advised numerous PhD students including Mert Toslali, Anthony Byrne, and Burak Aksar. Her lab maintains strong industry partnerships with IBM, Intel, AMD, and Oracle, and collaborates with academic institutions worldwide including Brown University, MIT, EPFL, and CEA-Tech in France. Dr. Coskun leads the Coskun Lab, which secured a $500K grant from Sandia National Labs for AI-based analytics in high performance computing systems, demonstrating the practical impact of her research on critical computing infrastructure.
Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.
Aviral Shrivastava is a Professor at the School of Computing and Augmented Intelligence, Arizona State University, leading the Make Programming Simple Lab. He holds a Ph.D. and M.S. from the University of California-Irvine (2006, 2002) and a Bachelor’s from IIT Delhi (1999). His research focuses on making programming simple for embedded and cyber-physical systems, with a particular interest in manycore and accelerated computing, software for CPS, and resilient/fault-tolerant computing. He has co-authored over 120 publications in top venues like DAC, ESWEEK, and ACM TECS, with more than 3000 citations and 5 granted patents. His work has been recognized with multiple awards, including the 2010 NSF CAREER award and best paper nominations. Research Areas: Embedded and Cyber-Physical Systems Compiler Design for Modern Architectures Resilient and Fault-Tolerant Computing Scientific Awards: 2010 NSF CAREER award DAC 2017 Best Paper Award Candidate VLSI 2016 Best Student Paper Award LCTES 2010 Second Highest Ranked Paper ASPDAC 2008 Best Paper Candidate Advising & Grants: He has mentored 9 Ph.D. and over 20 Masters students. His research has been funded by NSF, DOE, NIST, SFAZ, and industry partners, totaling $3.5M. He teaches courses on computer organization, architecture, and embedded systems, with student evaluations averaging over 4/5. He also serves as General Chair of Embedded Systems Week (ESWEEK) and holds editorial roles in IEEE ESL, ACM TCPS, and ACM TECS.
Dr. Ameer Abdelhadi is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on application-specific custom-tailored computer architectures, hardware-efficient deep learning, neurotechnology, and reconfigurable computing. He holds a PhD from the University of British Columbia and has held academic positions at the University of Toronto, Imperial College London, and Simon Fraser University, alongside industry experience in semiconductor design. Education: PhD in Computer Engineering (University of British Columbia, 2016). Research Interests: Hardware acceleration for machine learning and neurotechnology Reconfigurable computing and FPGAs/ASICs Asynchronous circuits and synchronization protocols VLSI physical design and CAD algorithms Publications span high-impact venues such as IEEE Journal of Solid-State Circuits, IEEE Hot Chips, and IEEE Micro. Notable achievements include the 2017 Best Paper Award at ASYNC for work on synchronization FIFOs. Teaching includes COMPENG 4DV4 (VLSI System Design) and ELECENG 4OI6B (Engineering Design). His lab focuses on advancing hardware systems for next-generation applications in AI and biomedical engineering.
Said Hamdioui serves as a full Professor in the Department of Computer Engineering within the Faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology. His research focuses on cutting-edge hardware architectures for neuromorphic computing and energy-efficient AI acceleration, with particular emphasis on memristor-based systems, emerging memory technologies, and fault-tolerant designs for edge applications. His research interests span Neuromorphic Computing , Memristor-Based Architectures , and Energy-Efficient AI Hardware , addressing critical challenges in hardware security, computation-in-memory, and reliable edge AI deployment. Recent work demonstrates significant advancements in RRAM/FeFET testing methodologies, spiking neural network implementations, and spin wave computing alternatives to traditional CMOS. His publications reveal strong trends toward real-world deployment of brain-inspired hardware with practical constraints like power efficiency, testability, and security. Award highlights include: DATE'20 Best Paper Award DFT'21 Outstanding Student Paper ETS 2021 Best Paper Award LATS 2018 & 2022 Best Paper Awards Professor Hamdioui actively contributes to the research community through editorial roles at IEEE Transactions on VLSI Systems , IEEE Design & Test , and Journal of Electronic Testing from 2017-2018. His leadership in multi-partner projects like CONVOLVE and NEUROKIT2E demonstrates strong industry-academia collaboration for edge AI solutions. Current work shows increasing focus on practical deployment challenges including in-field fault monitoring, security vulnerabilities in neuromorphic systems, and realistic brain simulation frameworks.
