Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.
Prof. Dr. Tobias Gemmeke is a University Professor at RWTH Aachen University's Faculty of Electrical Engineering and Information Technology, leading the Chair of Integrated Digital Systems and Circuit Design. His work focuses on neuromorphic computing, hardware accelerators, and energy-efficient electronics. He has pioneered advancements in FPGA-based computational neuroscience simulators, neuromorphic processor architectures, and sensor integration for industrial and medical applications. Research interests include time-domain computing, ReRAM reliability, and co-optimization of neural networks with hardware. Notable contributions include the neuroAIx framework for accelerated neuroscience simulations and energy-efficient ASIC designs for post-quantum cryptography. He actively explores memristive devices and domain generalization techniques for edge computing. Recent publications highlight innovations in spiking neural networks, sensor systems for plain bearings, and time-domain compute-in-memory engines. His work bridges theoretical neuroscience with practical hardware implementations, emphasizing scalability and real-time performance.
Abdulkadir C. Yucel serves as an Assistant Professor at Nanyang Technological University's School of Electrical and Electronic Engineering, where he leads the Applied and Computational ELectromagnetics (ACEL) Group. His research spans applied electromagnetics, radar imaging, and AI-driven electromagnetic analysis with applications in smart cities, neurotechnology, and quantum systems. Education: Ph.D. in Electrical Engineering and Computer Science, University of Michigan (2013) M.S. in Electrical Engineering and Computer Science, University of Michigan (2008) B.S. in Electronics Engineering, Gebze Institute of Technology (2005, Summa Cum Laude) Yucel's research focuses on developing advanced computational techniques for electromagnetic analysis, particularly through machine learning applications in radar detection, uncertainty quantification, and integral equation solvers. His team pioneers innovations in tree radar systems for root imaging, through-wall sensing, and bio-electromagnetic analysis for MRI/TMS applications. Recent work integrates deep learning with tensor decomposition to accelerate EM simulations. Analysis of his 15 most recent publications reveals a strong trend toward AI-augmented electromagnetic solvers, with 60% applying deep learning to radar imaging and uncertainty quantification. Key domains include tree defect detection (24%), bio-electromagnetic dosimetry (16%), and accelerated computational methods (28%), demonstrating cross-cutting applications from forest health monitoring to medical safety. Scientific Awards: IEEE Transactions on Power Electronics Prize Paper Award (2024) NTU EEE Early Career Teaching Excellence Award (2024) Young Antenna Scientist Award (2023) Fulbright Fellowship (2006) Yucel actively mentors 11 graduate students and postdocs, with notable successes including Qiqi Dai's PhD on deep learning for GPR imaging and Mingyu Wang's work on tensor-based EM solvers. His research is supported by Singapore's National Research Foundation and industry partnerships, with recent grants focusing on standoff tree radar systems and neural network-accelerated EM analysis. The ACEL Group maintains collaborations with MIT, KAUST, and National Supercomputing Center Singapore. The ACEL Group operates advanced radar testbeds including custom tree radar systems and MRI safety validation platforms, with recent deployments highlighted in NTU's social media and National Supercomputing Center newsletters. Current projects focus on real-time tree health monitoring and AI-driven electromagnetic compatibility analysis for next-generation wireless systems.
Said Hamdioui serves as a full Professor in the Department of Computer Engineering within the Faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology. His research focuses on cutting-edge hardware architectures for neuromorphic computing and energy-efficient AI acceleration, with particular emphasis on memristor-based systems, emerging memory technologies, and fault-tolerant designs for edge applications. His research interests span Neuromorphic Computing , Memristor-Based Architectures , and Energy-Efficient AI Hardware , addressing critical challenges in hardware security, computation-in-memory, and reliable edge AI deployment. Recent work demonstrates significant advancements in RRAM/FeFET testing methodologies, spiking neural network implementations, and spin wave computing alternatives to traditional CMOS. His publications reveal strong trends toward real-world deployment of brain-inspired hardware with practical constraints like power efficiency, testability, and security. Award highlights include: DATE'20 Best Paper Award DFT'21 Outstanding Student Paper ETS 2021 Best Paper Award LATS 2018 & 2022 Best Paper Awards Professor Hamdioui actively contributes to the research community through editorial roles at IEEE Transactions on VLSI Systems , IEEE Design & Test , and Journal of Electronic Testing from 2017-2018. His leadership in multi-partner projects like CONVOLVE and NEUROKIT2E demonstrates strong industry-academia collaboration for edge AI solutions. Current work shows increasing focus on practical deployment challenges including in-field fault monitoring, security vulnerabilities in neuromorphic systems, and realistic brain simulation frameworks.
Nicola Nicolici is a Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on methods and algorithms for the design of digital integrated circuits and systems, with significant contributions in manufacturing test, post-silicon validation and debug. His work has expanded to include embedded systems, low-energy computing, and custom hardware-accelerated computing systems. Professor Nicolici's research interests span multiple areas of digital system design and validation. His early work focused on manufacturing test methodologies and power-aware testing strategies for integrated circuits. More recently, he has made significant contributions to post-silicon validation techniques, including constrained-random stimuli generation, trace signal selection, and bit-flip detection. His research has evolved to address emerging challenges in embedded computing systems, low-energy design, and specialized hardware acceleration for various applications including deep neural networks and signal processing. His recent publications reveal a strong trend toward hardware acceleration for specialized computing tasks. The research spans matrix multiplication algorithms (Strassen and Karatsuba), memory system optimization (DDR5 calibration), FPGA-based radar processing, and neural network acceleration. His work consistently bridges theoretical algorithm development with practical hardware implementation considerations, particularly focusing on precision analysis, fault tolerance, and energy efficiency. The research demonstrates a clear progression from traditional digital circuit testing to more complex system-level validation and acceleration techniques. Professor Nicolici has been actively involved in teaching courses related to system-on-chip design and test, digital systems, and embedded systems. His teaching portfolio includes advanced courses such as System-on-Chip (SOC) Design and Test and Digital Systems Design , reflecting his expertise in the field. While specific grant information isn't detailed in the provided text, his extensive publication record suggests ongoing research funding support. His research has contributed significantly to the fields of digital circuit testing, post-silicon validation, and hardware acceleration. The work has practical applications in semiconductor manufacturing, embedded systems design, and specialized computing architectures. His recent focus on neural network acceleration and memory system optimization reflects the evolving landscape of computer architecture research.
Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.
Irith Pomeranz is the Cadence Professor of Electrical and Computer Engineering at Purdue University's College of Engineering. Her research focuses on advanced testing methodologies for VLSI circuits, including functional test compaction, fault diagnosis, and built-in self-test (BIST) techniques. She is affiliated with the Department of Electrical and Computer Engineering and has contributed extensively to improving test efficiency and fault coverage in digital circuits. Her work addresses challenges such as aging effects, transition faults, and path delay faults, with a particular emphasis on practical implementations for industrial applications. Key areas of interest include modular test sequences, configuration-based compaction, and dynamic testing strategies for in-field environments. She has developed algorithms for dual-target diagnostic testing and synchronization mechanisms for online fault detection in logic blocks. Research Trends in her publications emphasize innovations like storage-based BIST schemes, adaptive test scheduling, and shared test data architectures. These advancements aim to reduce test data volume, improve fault coverage, and enhance reliability in modern integrated circuits. Her work often bridges theoretical foundations and practical hardware implementations. Grants & Advising : While specific grants or student advisees are not listed, her prolific publication record indicates active involvement in research projects and graduate supervision within Purdue's ECE department. Labs & Teams : Her contributions are likely tied to Purdue's VLSI and testing research groups, though specific lab affiliations are not detailed in the provided text.
Swiss Federal Institute of Technology in LausanneSwitzerland
Xuming He is an Associate Professor at the School of Information Science and Technology (SIST), ShanghaiTech University, where he leads the PLUS Lab. His research spans computer vision and machine learning with a focus on developing algorithms that operate effectively under limited supervision and evolving data conditions. His core research interests include weakly-supervised and few-shot learning for scenarios with sparse annotations, continual learning frameworks for knowledge retention during sequential task acquisition, semantic segmentation techniques for scene understanding, and multimodal vision-language representations. He emphasizes interpretable machine learning to build transparent AI systems capable of human-understandable reasoning, addressing critical challenges in model trustworthiness and deployment reliability. Recent publications reveal strong trends toward novel class discovery in long-tailed recognition scenarios, physics-informed generative modeling for scientific applications, and robust segmentation under distribution shifts. His work increasingly integrates large language models for multimodal reasoning while maintaining focus on efficiency in resource-constrained environments like robotic grasping and medical imaging analysis. He actively mentors students, having supervised Qian He to PhD completion and Chuanyang Hu to Master's degree in 2023. He welcomes prospective graduate students through ShanghaiTech's Computer Science & Technology program and offers undergraduate research projects requiring minimum six-month commitments. The PLUS Lab under his direction drives innovation in learning under supervision constraints, with recent work spanning medical tumor analysis, cross-view geolocation, photonic computing, and semiconductor design verification. The lab's research bridges theoretical advances with practical applications across healthcare, robotics, and scientific discovery domains.
Azadeh Davoodi is a Vilas Distinguished Achievement Professor and Associate Chair of Undergraduate Studies in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. Her research focuses on Electronic Design Automation (EDA), integrated circuit debug, and machine learning applications in VLSI design. She holds editorial roles in journals like IEEE TCAD and ACM TRETS, and has chaired major conferences such as ISPD 2015 and served on technical program committees for DAC, ICCAD, and others. Education: PhD in Electrical Engineering, University of Maryland-College Park (2006) Research Interests: Machine learning for VLSI chip design VLSI design automation for machine learning IC-CAD for emerging nanotechnologies Hardware security Recent Research Trends: Her work bridges machine learning and hardware design, with publications on neural network optimization, distributed inference, and explainable AI for circuit design. She emphasizes energy-efficient CNNs, latency reduction in edge computing, and security in split manufacturing. Awards: 2025 DATE Best Paper Candidate 2024 Vilas Distinguished Achievement Professor 2015 ACM Best Paper Award 2011 NSF CAREER Award Service and Grants: Leads NSF-funded projects on explainable ML for CAD and holds grants for distributed neural network synthesis. Her service includes roles as IEEE HKN member and editorial board positions. Labs/Teams: Engages in interdisciplinary research teams at UW-Madison, focusing on EDA innovation and hardware-software co-design.
Guido Masera is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he has been actively involved in teaching and research for over two decades. He serves as a Member of the Board of Directors, Member of the GEDI Observatory for Gender Equality, Diversity and Inclusion, and Member of the Permanent University Observatory for monitoring the academic supply chain. His research interests span across channel decoders, circuits for communications, cryptography, deep learning, digital integrated circuits, field programmable gate arrays (FPGA), and hardware design. His work focuses on VLSI architectures for image and video coding, digital architectures for error correcting codes, application specific approximate computing, VLSI architectures for machine learning, digital architectures for bio-inspired processing, digital architectures for post-quantum cryptography, bio-inspired electronics for robotics and biomedical applications, RISC-V extensions and hardware accelerators, and circuit architectures for efficient machine learning and artificial intelligence. His recent publications (2025) demonstrate a strong focus on RISC-V architecture, particularly in the context of cryptographic implementations, hardware security, and post-quantum cryptography. His research group VLSILAB is actively engaged in cutting-edge research in hardware security, efficient processor design, and specialized computing architectures. Among his notable recognitions are the Premio Francesco Carassa awarded by the Telecommunications and Information Technologies Group Association (gtti) in 2010, and his recognition as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) since 2007. He also serves as an Associate Editor for several prestigious journals including ELECTRONICS (2019-present), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (2015-2019), and IET CIRCUITS, DEVICES & SYSTEMS (2013-2016). Professor Masera has advised numerous PhD students working on advanced topics in VLSI design, post-quantum cryptography, hardware accelerators, and machine learning implementations. His current research projects include ISOLDE (2023-2026) and TRISTAN (2022-2025), both EU-funded projects focused on RISC-V technology and domain-specific ecosystems. He leads the VLSILAB research group at the Department of Electronics and Telecommunications, which focuses on cutting-edge research in VLSI architectures, hardware security, and specialized computing systems. The group collaborates with industry partners and participates in major European research initiatives.
Tsung-Yi Ho is a Professor in the Department of Computer Science at National Tsing Hua University, Taiwan. He holds the Hans Fischer Fellowship at the Technical University of Munich's Institute for Advanced Study (TUM-IAS). His primary research focuses on design automation for microfluidic biochips and nanometer integrated circuits, emphasizing reliability, optimization, and interdisciplinary applications in bioengineering. Ho received his Ph.D. in Electrical Engineering from National Taiwan University in 2005. He has held positions at National Cheng Kung University and National Chiao Tung University before joining National Tsing Hua University. His work bridges algorithmic design with practical biochip fabrication, addressing challenges like contamination control, routing optimization, and fault tolerance in microfluidic systems. His research interests span design automation for emerging technologies, including paper-based biochips and 3D microfluidic architectures. He has pioneered methods for integrating hardware-software co-design principles into biochip development, enhancing both functionality and reliability. His contributions include novel routing algorithms, contamination mitigation techniques, and reliability-aware synthesis frameworks. Ho has authored over 100 publications, including influential papers in IEEE Transactions on CAD and ACM journals. He serves on the editorial boards of multiple top-tier journals and chairs professional chapters for ACM and IEEE. His awards include the Humboldt Research Fellowship, Dr. Wu Ta-You Memorial Award, and Best Paper Awards at VLSI Test Symposium and IEEE Transactions on CAD. His current projects involve optimizing control-fluidic co-design for paper-based biochips and developing AI-driven frameworks for microfluidic functionality prediction. He collaborates widely, leading cross-disciplinary initiatives at TUM-IAS and Taiwan's academic institutions.
Kanad Basu is an Associate Professor in the Department of Electrical, Computer, and Systems Engineering at The University of Texas at Dallas, Jonsson School of Engineering and Computer Science. He leads the Trustworthy and Intelligent Embedded Systems (TIES) lab, focusing on hardware security, reliability, and emerging computing paradigms. His research spans AI hardware, quantum computing, functional safety, and hardware-based security validation. Research Interests: His work emphasizes improving the trustworthiness of modern hardware systems. Key areas include hardware security (e.g., side-channel analysis, hardware trojans), functional safety in AI accelerators, quantum computing security and verification, and post-silicon validation techniques. He combines formal methods, machine learning, and hardware design to address vulnerabilities in SoCs, DNN accelerators, and quantum systems. Publication Trends: Recent publications (2023–2025) show a strong focus on interdisciplinary research, integrating AI/ML with hardware security, quantum computing, and functional safety. There is a growing emphasis on using large language models for assertion generation, symbolic execution for hardware fuzzing, and graph neural networks for quantum circuit analysis. His work frequently appears in top venues like DAC, DATE, HOST, ISVLSI, and IEEE journals. Scientific Awards: NSF CAREER Award, 2025 IEEE Top Picks in Test and Reliability, 2024 and 2023 Multiple Hack@DAC Prizes (2nd and 3rd) Best Paper Award at VLSI Design 2011 Assistant Professor Award at UTD Jonsson School, 2024 Nominated for Blavatnik Awards for Young Scientists, 2019 Advising and Grants: Dr. Basu has mentored numerous PhD, MS, and undergraduate students, many of whom have published in top-tier venues. He leads the TIES lab, which has received significant recognition, including the NSF CAREER Award. He actively collaborates across disciplines, advising students on topics ranging from quantum computing to AI hardware and functional safety. His lab produces high-impact research with real-world applications in automotive, cloud, and embedded systems. Labs and Teams: He leads the Trustworthy and Intelligent Embedded Systems (TIES) lab at UT Dallas, which fosters innovation in hardware security and reliability. The lab has produced award-winning work, including second prize at HACK@DAC 2025. He also serves on technical committees for IEEE DATE and HOST, and acts as Hardware Hacking Chair for IEEE HOST, indicating strong leadership in the hardware security community.
Labros Bisdounis is a Professor at the Department of Electrical and Computer Engineering, University of the Peloponnese, Greece. He previously held positions at the Technological Educational Institute of Western Greece, including Associate Professor, Full Professor, and Dean of the School of Technological Applications (2016–2018). He has extensive industry experience as a senior research engineer and project manager at Intracom S.A. (2000–2008), focusing on VLSI circuits and telecom applications. His research interests include CMOS circuit timing/power modeling, low-power/high-speed design, MOSFET modeling, and sensor applications. He has authored over 30 papers with 740+ citations and is an IEEE member. Education: Diploma in Electrical Engineering (1992), University of Patras Ph.D. in Electrical Engineering (1999), University of Patras Research Interests: CMOS circuit timing and power dissipation modeling Deep-submicron/nano-CMOS circuit design MOSFET device modeling Low-power embedded systems and SoC Sensor applications and organic electronics Leadership Roles: Dean of the School of Engineering, University of the Peloponnese (2023–present) Director of Training & Lifelong Learning Centre (2019–2019) Board Member, Hellenic NARIC (2016–2019) Collaborations: Active at the Hellenic Open University as a tutor in Computer Architecture and Digital Systems modules. Co-developed the AETHER framework for pervasive computing and contributed to energy-aware SoC designs for 5 GHz WLANs.
Mehdi Sadi is an Assistant Professor of Electrical and Computer Engineering at Auburn University's College of Engineering. He holds a Ph.D. from the University of Florida, an M.S. from the University of California-Riverside, and a B.S. from Bangladesh University of Engineering and Technology. His research focuses on secure and reliable system-on-chip design, AI/ML-driven VLSI CAD/EDA, neuromorphic hardware, and emerging post-CMOS computing technologies. Notable achievements include earning the NSF CAREER Award for chiplet-based design optimization and a $175k NSF grant for magnetic RAM research. His work integrates machine learning with hardware co-design to enhance AI accelerators' performance, energy efficiency, and security. Recent projects include adversarial attack mitigation on AI hardware and reliability analysis of neuromorphic systems. Dr. Sadi's contributions span chiplet architecture, memory systems (e.g., STT-MRAM/SOT-MRAM), and fault-tolerant computing. He actively publishes on topics like skyrmion logic gates and TRNG implementations using MRAM. His work bridges theoretical machine learning advancements with practical hardware implementations, addressing critical challenges in next-generation computing systems.
University of Maryland, Baltimore CountyUnited States
Riadul Islam serves as an Assistant Professor in the Department of Computer Science and Electrical Engineering at the University of Maryland, Baltimore County (UMBC), maintaining his primary office in room 316 of the Information Technology and Engineering (ITE) Building. His academic appointment focuses on hardware design and verification within the institution's engineering framework. His educational qualifications include: Ph.D. in Computer Engineering from UCSC (2017) M.A.Sc. in Electrical and Computer Engineering from Concordia University, Montreal (2011) B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (2007) Professor Islam's research centers on VLSI CAD tools and low-power digital/mixed-signal IC design , with significant contributions to current-mode clock networks, vehicular security systems, and error-robust circuit architectures. His work increasingly integrates machine learning for design automation while exploring neuromorphic computing applications and secure hardware implementations. This multidisciplinary approach bridges traditional IC design with modern AI-driven optimization techniques. Analysis of his 2023-2025 publications reveals three dominant research thrusts: (1) Machine learning applications in early-stage Design Rule Checking (DRC) prediction and clock network optimization, (2) Graph-based intrusion detection systems for automotive networks (particularly CAN bus security), and (3) Event-based vision systems and neuromorphic computing architectures. These areas demonstrate consistent innovation in merging hardware design with AI/ML methodologies for enhanced system reliability and efficiency. He directs the UMBC VLSI and SoC Research Group , which develops energy-efficient clocking networks, secure vehicular communication protocols, and compute-in-memory architectures. The lab maintains active collaboration with industry partners on hardware security and neuromorphic computing initiatives while supporting graduate student research in cutting-edge IC design methodologies.
