Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.
Vijay Laxmi is a Professor in the Department of Computer Science and Engineering at Malaviya National Institute of Technology (MNIT) Jaipur, India. With over a decade of active research publication from 2014-2024, Dr. Laxmi has established themselves as a prominent researcher in network security, Android security systems, and Network-on-Chip architectures. Their work demonstrates consistent collaboration with Manoj Singh Gaur and numerous doctoral students at MNIT Jaipur. Dr. Laxmi's research interests span Network Security, Android Security, Malware Analysis, Network-on-Chip Architectures, Routing Protocols, Side-Channel Attacks, Wireless Networks, and Mobile Security. Their work bridges theoretical security frameworks with practical implementations, particularly in mobile and embedded systems. Recent publications indicate a growing focus on AI-based security approaches including GAN applications for fuzzing and deep learning for image dehazing. The research trajectory shows increasing sophistication in security analysis techniques, evolving from basic malware detection to advanced side-channel attack analysis and sophisticated network security protocols. Recent publications demonstrate expertise in both theoretical frameworks and practical implementations with applications in real-world security challenges. Dr. Laxmi has mentored numerous graduate students including Vineeta Jain, Anugrah Jain, Sonal Yadav, Mohit Singh, and Gaurav Singal, who appear as co-authors across multiple publications. Their collaborative network extends to researchers at international institutions, indicating strong academic connections beyond their home institution.
Professor Bharat Bhuva is a faculty member in the School of Engineering at Vanderbilt University, holding the position of Professor of Electrical Engineering and Computer Engineering . His research focuses on radiation effects on integrated circuits, semiconductor device modeling, and VLSI design, with an emphasis on advancing the resilience of nanoscale electronics against single-event effects and total-ionizing-dose damage. He also investigates emerging technologies like FinFET and FDSOI for improved radiation hardness and performance. Education: Ph.D. in Electrical Engineering, North Carolina State University M.S. in Electrical Engineering, North Carolina State University B.S. in Electrical Engineering, Maharaja Sayajirao University Research Interests: Professor Bhuva’s work spans computer-aided design tools, semiconductor process modeling, and the mitigation of radiation-induced failures in advanced integrated circuits. His studies address challenges posed by scaling to smaller technology nodes (e.g., 3-nm FinFET) and the impact of environmental factors like temperature, bias conditions, and neutron exposure on circuit reliability. Key areas include multicell upsets, single-event upset (SEU) cross-section analysis, and the efficacy of radiation-hardened-by-design (RHBD) techniques. Awards & Recognition: None explicitly listed in the provided text. However, his extensive publications in top-tier journals like IEEE Transactions on Nuclear Science highlight his contributions to the field. Grants & Advising: Advises on projects related to advanced semiconductor technologies and radiation effects. His research has been supported by grants from institutions focusing on space electronics and nanotechnology. No specific grant details or student advisees are listed. Labs & Teams: Likely affiliated with Vanderbilt’s Cyber-physical Systems and Nano Science and Technology research neighborhoods, though specific lab names are not mentioned in the text.
Suman Datta is a Professor at the Georgia Institute of Technology , holding the Joseph M. Pettit Chair in Advanced Computing and Georgia Research Alliance Eminent Scholar titles. He has a joint appointment with the School of Materials Science and Engineering. Education : B.Tech in Electrical Engineering from IIT Kanpur; Ph.D. in Electrical and Computer Engineering from the University of Cincinnati. Prior Appointments : Stinson Endowed Chair Professor of Nanotechnology at University of Notre Dame (2015–2022); Professor at Penn State (2007–2015); Intel Corporation (1999–2007) in Advanced Transistor Group. Research Interests : His work focuses on high-performance heterogeneous computing using advanced CMOS and beyond-CMOS semiconductors. Key areas include ferroelectric field-effect transistors (FeFETs) , cryogenic computing , in-memory computing , and brain-inspired computing . He explores materials like ferroelectric gate stacks , insulator-to-metal phase transition oxides , and high-mobility oxides for next-generation compute architectures. Recent Article Trends : His group’s publications emphasize BEOL-compatible oxide transistors , negative capacitance , radiation-resilient devices , and machine learning-aided modeling . Subfields include low-voltage memory , 3D Ising machines , dynamic logic at cryogenic temperatures , and monolithic integration of power delivery systems. Scientific Awards : IEEE Fellow (2013) for contributions to transistor technologies NAI Fellow (2016) for societal impact via patents Intel Achievement Award (2003) for high-k/metal gate CMOS Intel Logic Technology Quality Award (2002) for Tri-gate transistors SEMI Award (2012) for high-k dielectrics Penn State Outstanding/ Premier Research Awards (2012, 2015) Advising & Grants : He has mentored students like Wriddhi Chakraborty , Khandker Akif Aabrar , and Sourav Dutta . His research is funded by SRC , DARPA , and NSF , including leadership of the ASCENT and EXCEL centers. Labs & Collaborations : Datta directs the STAR Lab at Georgia Tech, which specializes in atomistic modeling , nanofabrication , and compact model development . The lab collaborates with industry giants like Intel , Micron , and IBM through the ASCENT center.
Prof. Dr. Amelie Hagelauer holds a professorship in Micro- and Nanosystem Technology at the TUM School of Computation, Information and Technology, Technical University of Munich. Her work focuses on advanced electronics and systems integration across quantum computing hardware, resistive memory technologies, and high-frequency RF systems. She has contributed to innovations in superconducting qubit readout architectures, multi-level RRAM designs, and 3D-integrated CMOS-compatible quantum devices. Research interests span quantum hardware design, nanoelectronic devices, RF front-end systems, and emerging memory technologies. Her work emphasizes practical implementation challenges such as low-power operation, high-voltage handling in RF switches, and wafer-scale fabrication processes. Recent projects include D-band radar systems, energy-efficient 60 GHz transceivers, and antenna tuning solutions for 5G applications. Publications from 2023-2025 showcase advancements in resistive switching device characterization, mitigation of TLS losses in superconducting qubits, and reconfigurable AI accelerators using RRAM-based digital twins. Her work bridges theoretical device physics with practical integrated circuit design, addressing scalability and reliability in next-gen electronics. Awards and grants: None explicitly listed in provided texts. Active collaborations include EU-funded projects on quantum computing platforms and TUM's Electronic Photonic Integration initiatives. Leads research teams in microsystem technology with emphasis on cross-disciplinary approaches combining CMOS processes, MEMS, and quantum engineering.
Dr. Chih-Hung (James) Chen is a Professor in the Department of Electrical & Computer Engineering at McMaster University. His research focuses on noise-related issues in semiconductor devices, low-noise circuit design for medical and communication applications, and thermal noise characterization in nano-scale transistors. He holds senior member status in IEEE and is a licensed Professional Engineer in Ontario. Education: Ph.D., McMaster University, 2002 M.A.Sc., Simon Fraser University, 1997 B.Sc., National Central University, Taiwan, 1991 Research interests include biomedical technologies, microelectronics & VLSI, and digital/smart systems. He has collaborated with companies like Sony Corporation, United Microelectronics Corporation, and Focus Microwaves. His work is supported by grants from the Canada Foundation for Innovation (CFI), NSERC, and the Ontario Innovation Trust (OIT). Notable achievements include serving on the International Advisory Committee of the International Conference on Noise and Fluctuations (2015) and as an editor for the Journal of Low Power Electronics and Applications since 2022. Teaching includes courses like Analysis and Design of RF ICs for Communications and Electronic Devices and Circuits 2. His research lab focuses on advancing noise measurement techniques and designing ultra-low-power analog circuits for emerging applications.
Prof. Dr. Tobias Gemmeke is a University Professor at RWTH Aachen University's Faculty of Electrical Engineering and Information Technology, leading the Chair of Integrated Digital Systems and Circuit Design. His work focuses on neuromorphic computing, hardware accelerators, and energy-efficient electronics. He has pioneered advancements in FPGA-based computational neuroscience simulators, neuromorphic processor architectures, and sensor integration for industrial and medical applications. Research interests include time-domain computing, ReRAM reliability, and co-optimization of neural networks with hardware. Notable contributions include the neuroAIx framework for accelerated neuroscience simulations and energy-efficient ASIC designs for post-quantum cryptography. He actively explores memristive devices and domain generalization techniques for edge computing. Recent publications highlight innovations in spiking neural networks, sensor systems for plain bearings, and time-domain compute-in-memory engines. His work bridges theoretical neuroscience with practical hardware implementations, emphasizing scalability and real-time performance.
Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.
Aviral Shrivastava is a Professor at the School of Computing and Augmented Intelligence, Arizona State University, leading the Make Programming Simple Lab. He holds a Ph.D. and M.S. from the University of California-Irvine (2006, 2002) and a Bachelor’s from IIT Delhi (1999). His research focuses on making programming simple for embedded and cyber-physical systems, with a particular interest in manycore and accelerated computing, software for CPS, and resilient/fault-tolerant computing. He has co-authored over 120 publications in top venues like DAC, ESWEEK, and ACM TECS, with more than 3000 citations and 5 granted patents. His work has been recognized with multiple awards, including the 2010 NSF CAREER award and best paper nominations. Research Areas: Embedded and Cyber-Physical Systems Compiler Design for Modern Architectures Resilient and Fault-Tolerant Computing Scientific Awards: 2010 NSF CAREER award DAC 2017 Best Paper Award Candidate VLSI 2016 Best Student Paper Award LCTES 2010 Second Highest Ranked Paper ASPDAC 2008 Best Paper Candidate Advising & Grants: He has mentored 9 Ph.D. and over 20 Masters students. His research has been funded by NSF, DOE, NIST, SFAZ, and industry partners, totaling $3.5M. He teaches courses on computer organization, architecture, and embedded systems, with student evaluations averaging over 4/5. He also serves as General Chair of Embedded Systems Week (ESWEEK) and holds editorial roles in IEEE ESL, ACM TCPS, and ACM TECS.
Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She also serves as the Acting Associate Dean for Research at the Grainger College of Engineering. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a collaboration between the University of Illinois, North Carolina State University, and Penn State University. Education: Ph.D. in Electrical Engineering, University of California, Berkeley, 1992 M.S. in Electrical Engineering, Stanford University B.S. in Electrical Engineering, Cornell University (with distinction) Research Interests: Her research focuses on machine learning applications in electronics, ESD-robust high-speed I/O circuit design, compact modeling, behavioral modeling of circuits, and CDM-ESD protection for advanced packaging technologies. Scientific Awards: IEEE Fellow for contributions to electrostatic discharge reliability of integrated circuits Best Student Paper Award, IEDM Outstanding and Best Paper Awards, EOS/ESD Symposium Technical Excellence Award, SRC NSF CAREER Award IBM Faculty Award ESD Association’s Industry Pioneer Recognition Award Advising and Grants: She supervises graduate and undergraduate researchers, primarily focusing on those with strong academic records and relevant experience. Her work is supported by NSF and other prominent organizations. Labs and Teams: She leads the CAEML center, which aims to apply machine learning to optimize microelectronic circuits and systems, enhancing design automation and reliability.
Said Hamdioui serves as a full Professor in the Department of Computer Engineering within the Faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology. His research focuses on cutting-edge hardware architectures for neuromorphic computing and energy-efficient AI acceleration, with particular emphasis on memristor-based systems, emerging memory technologies, and fault-tolerant designs for edge applications. His research interests span Neuromorphic Computing , Memristor-Based Architectures , and Energy-Efficient AI Hardware , addressing critical challenges in hardware security, computation-in-memory, and reliable edge AI deployment. Recent work demonstrates significant advancements in RRAM/FeFET testing methodologies, spiking neural network implementations, and spin wave computing alternatives to traditional CMOS. His publications reveal strong trends toward real-world deployment of brain-inspired hardware with practical constraints like power efficiency, testability, and security. Award highlights include: DATE'20 Best Paper Award DFT'21 Outstanding Student Paper ETS 2021 Best Paper Award LATS 2018 & 2022 Best Paper Awards Professor Hamdioui actively contributes to the research community through editorial roles at IEEE Transactions on VLSI Systems , IEEE Design & Test , and Journal of Electronic Testing from 2017-2018. His leadership in multi-partner projects like CONVOLVE and NEUROKIT2E demonstrates strong industry-academia collaboration for edge AI solutions. Current work shows increasing focus on practical deployment challenges including in-field fault monitoring, security vulnerabilities in neuromorphic systems, and realistic brain simulation frameworks.
Nicola Nicolici is a Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on methods and algorithms for the design of digital integrated circuits and systems, with significant contributions in manufacturing test, post-silicon validation and debug. His work has expanded to include embedded systems, low-energy computing, and custom hardware-accelerated computing systems. Professor Nicolici's research interests span multiple areas of digital system design and validation. His early work focused on manufacturing test methodologies and power-aware testing strategies for integrated circuits. More recently, he has made significant contributions to post-silicon validation techniques, including constrained-random stimuli generation, trace signal selection, and bit-flip detection. His research has evolved to address emerging challenges in embedded computing systems, low-energy design, and specialized hardware acceleration for various applications including deep neural networks and signal processing. His recent publications reveal a strong trend toward hardware acceleration for specialized computing tasks. The research spans matrix multiplication algorithms (Strassen and Karatsuba), memory system optimization (DDR5 calibration), FPGA-based radar processing, and neural network acceleration. His work consistently bridges theoretical algorithm development with practical hardware implementation considerations, particularly focusing on precision analysis, fault tolerance, and energy efficiency. The research demonstrates a clear progression from traditional digital circuit testing to more complex system-level validation and acceleration techniques. Professor Nicolici has been actively involved in teaching courses related to system-on-chip design and test, digital systems, and embedded systems. His teaching portfolio includes advanced courses such as System-on-Chip (SOC) Design and Test and Digital Systems Design , reflecting his expertise in the field. While specific grant information isn't detailed in the provided text, his extensive publication record suggests ongoing research funding support. His research has contributed significantly to the fields of digital circuit testing, post-silicon validation, and hardware acceleration. The work has practical applications in semiconductor manufacturing, embedded systems design, and specialized computing architectures. His recent focus on neural network acceleration and memory system optimization reflects the evolving landscape of computer architecture research.
Wenjing Rao is an Associate Professor at the Department of Electrical and Computer Engineering, College of Engineering, University of Illinois at Chicago (UIC). Her research focuses on VLSI test, fault-tolerance, reliability, and hardware security in emerging nanoelectronic systems. Education: Ph.D. in Computer Science from University of California, San Diego (2008) B.S. in Computer Science from Peking University (2001) Her work explores novel computation paradigms through physical unclonable functions (PUFs), defect-tolerant logic implementation, and scalable fault tolerance in many-processor arrays. Publications emphasize hardware security, reconfiguration strategies, and reliability challenges in nanoscale architectures. Notable honors include the 2017 Harold A. Simon Award for Excellence in Teaching and the 2012 NSF CAREER Award. She has contributed to key journals like IEEE Transactions on Computer-Aided Design and conferences including DATE, ASPDAC, and NANOARCH.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Prof. Jörg Henkel serves as Professor and Head of the Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany. Previously a Senior Research Staff Member at NEC Laboratories Princeton, he holds a PhD from Braunschweig University (Summa cum Laude) and directs major research initiatives including the DFG's SPP 1500 program on 'Dependable Embedded Systems'. Research Focus: His work centers on embedded systems dependability , low-power design , and adaptive computing architectures . Through the SPP 1500 program and TR89 Collaborative Research Center, he pioneers fault-tolerance techniques and runtime adaptation for safety-critical applications, addressing energy efficiency challenges in hardware/software co-design. Scientific Recognition: IEEE Fellow (for contributions to low-power dependable embedded systems) Multiple Best Paper Awards (DATE 2008, ICCAD 2009, Codes+ISSS 2011/2014/2015) DAC 2014 Designer Track Best Poster Award DATE 2013 Best IP Award Leadership & Service: As Editor-in-Chief of IEEE Design&Test Magazine and former ACM TECS EiC, he shapes scholarly discourse. He has chaired premier conferences (ICCAD 2012/2013, ESWeek 2016) and delivered 10+ keynotes on embedded systems reliability. His DFG-coordinated projects secure substantial funding for national collaborative research. Technical Infrastructure: Leads the Chair for Embedded Systems (CES) within KIT's Institute of Technical Informatics, driving innovation in hardware/software co-design and invasive computing through the TR89 consortium.
