Dr. Mohamed Hassan is an Assistant Professor in the Department of Electrical & Computer Engineering at McMaster University. His research focuses on Cyber-Physical Systems-on-Chip (iCPSoCs) , emphasizing design, analysis, and deployment for critical domains like Unmanned Aerial Vehicles (UAVs), Autonomous Cars, and healthcare systems. Key research areas include hardware/software codesign, real-time systems, embedded systems, and security. He teaches courses such as COMPENG 4DM4 (Computer Architecture) and COMPENG 4DS4 (Embedded Systems) . His work bridges foundational theories (e.g., scheduling, AI) with infrastructure-level innovations (e.g., compilers, memory systems). The Fanos Research Lab he leads explores interdisciplinary solutions for efficient CPS-on-Chip, addressing challenges in multicore predictability, memory latency, and edge computing. Recent contributions include frameworks for explainable memory-centric workloads and techniques to accelerate TinyML inference. Dr. Hassan serves on Technical Program Committees for conferences like RTAS and OSPERT, highlighting his role in advancing real-time embedded systems research.
Vincent John Mooney III is an Associate Professor at the School of Electrical and Computer Engineering and an Adjunct Associate Professor at the School of Computer Science, Georgia Institute of Technology. His research focuses on Hardware-Software Co-Design , Cyber Physical Systems Security , and Low-Power Architectures . He has authored numerous publications on topics such as probabilistic computing, hardware security, and embedded systems design. Dr. Mooney has received prestigious awards including the NSF Career Award , National Semiconductor Fellowship , and ARCS Best Paper Award . Education: Ph.D. in Electrical Engineering (1998), Stanford University MA in Philosophy (1997), Stanford University MS in Electrical Engineering (1994), Stanford University Certificate of Graduate Study (1992), University of Navarra BS in Electrical Engineering and Computer Science (1991), Yale University Research interests span hardware/software codesign, cybersecurity in embedded systems, and synthesis of reconfigurable architectures. His recent work includes Gridtrust for decentralized supply chain cybersecurity and COPPER for computation obfuscation. Dr. Mooney has supervised numerous Ph.D. students and held leadership roles in conferences such as HOST and CASES . Scientific awards include NSF Career Award (2000) National Semiconductor Fellowship (1997-1998) AT&T Engineering Scholarship Program (1987-1991) NCAA Postgraduate Scholar (1991) Senior Member, IEEE (2003) ARCS 2012 Best Paper Award Advising and grants highlight his mentorship of students like Jun Cheol Park and Yudong Tan , along with grants such as the U.S. Air Force Summer Faculty Fellowship (2007). He leads the Hardware/Software Codesign for Security Group at Georgia Tech and has contributed to advancements in real-time operating systems and deadlock detection algorithms.
Dr. Farhad Merchant is an Assistant Professor of Innovative Computer Architecture at the Bernoulli Institute, University of Groningen, since July 2024. Previously, he served as a Lecturer (Assistant Professor) at Newcastle University (2022–2024) and held research roles at Bosch Research, NTU, and RWTH Aachen University. His research focuses on emerging technology-based computing and hardware-oriented security, including neuromorphic architectures, in-memory computing, and secure hardware design. Education: PhD in Electronics Engineering from the Indian Institute of Science, Bangalore, with a DAAD-funded visit to RWTH Aachen University. He also holds industry experience from Bosch Research. Research Interests : - Hardware Security - Neuromorphic Computing - Algorithm-Architecture Co-design - Reconfigurable Computing - Computer Arithmetic Projects : - Coordinator for the REACT project (2025–2029): Focuses on self-aware neuromorphic architectures. - Principal Investigator for Privacy-Preserving Computer Architectures (CogniGron, 2025–2029). - Completed BioNanoLock project (DFG-funded, focusing on bio-nanoelectronic security). Awards : - Best Paper Awards at ISQED 2022, NEWCAS 2023, and VLSI-DAT 2024. - Minerva Fellowship (Technion, Israel), HiPEAC Technology Transfer Award (2019). He co-founded the SeHAS workshop (since 2019) and serves on editorial and program committees for major conferences like DAC, ISLPED, and VLSI-SoC.
Patrick H. Madden is an Associate Professor and Director of the MS Information Systems program at the School of Computing, Binghamton University. His research focuses on combinatorial optimization, VLSI physical design automation, and algorithmic solutions for NP-Hard problems. He is also involved in interdisciplinary work in cryptography and biology-related optimization. Education: BS and MS from New Mexico Institute of Mining and Technology PhD from University of California, Los Angeles (UCLA) Professional Roles: Chair of ACM/SIGDA (Design Automation Special Interest Group) Chair of Design Automation Conference (DAC) Sponsors Committee Advisor to Binghamton ACM Student Chapter Coach for ICPC Programming Contest Teams Member of Watson School Graduation Committee Research Contributions: Leads the Optimality Research Group, developing optimization algorithms for VLSI CAD and medical software applications. Notable contributions include the Feng Shui placement tool and medical reference apps for iOS/Android platforms. Awards: SUNY Chancellor's Award for Excellence in Professional Service (2015) Grants & Collaborations: Collaborates with Prof. Monte McCollum (Cinema Department) on hybrid cinema projects and Dr. Joshua Steinberg (Physician) on medical software. Active in ACM committees and EDA conferences (DAC, ICCAD, ISPD). Labs/Teams: Directs the Optimality Research Group and oversees medical software collaborations through CS441/580 projects.
Lisa Wills serves as Assistant Professor of Computer Science at Duke University's Trinity College of Arts & Sciences and holds a joint appointment in Electrical and Computer Engineering at the Pratt School of Engineering since 2019. Her research bridges computer architecture and domain-specific applications, with a focus on hardware acceleration for computationally intensive fields. Dr. Wills earned her Ph.D. from Columbia University in 2014. Her academic journey reflects a deep commitment to advancing hardware-software co-design methodologies for real-world computational challenges. Her research centers on developing efficient hardware accelerators for big data analytics, particularly in genomics, graph processing, and database systems. She pioneers frameworks that simplify accelerator deployment while tackling critical bottlenecks in genomic data analysis, protein structure prediction, and privacy-preserving computing. Current work focuses on hardware-aware machine learning systems and energy-efficient architectures for emerging AI applications. Analysis of her publication record reveals a clear trajectory: from foundational work in database processing units (2014-2016) to specialized genomic accelerators (2019-2021), then evolving toward ML-enhanced design automation (2022-2023) and cutting-edge architectural abstractions (2024-2025). Her research consistently targets the intersection of hardware efficiency and domain-specific computational demands, with increasing emphasis on AI/ML workloads. Google ML and Systems Junior Faculty Award (2025) Dr. Wills actively mentors doctoral students including Chris Kjellqvist (lead architect of Beethoven accelerator framework), Mason Ma (PyTFHE FHE framework), and Mansi Choudhary (COCOSSim accelerator simulator). Her research is supported by significant grants including the NSF AI Institute: Athena ($20M, 2021-2027), Meta-funded ProSE accelerator project (2023-2026), and NSF CAREER award (2021-2026), totaling over $25M in active funding. She directs the APEX Lab (Application-driven Programmable Efficient Accelerated Systems), which develops open-source frameworks like Beethoven for FPGA/ASIC accelerator deployment and focuses on lowering barriers for non-hardware researchers to leverage custom acceleration in genomics, AI, and big data applications.
David Zhigang Pan is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He also holds the Silicon Laboratories Endowed Chair. Prior to joining UT Austin, he was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His academic journey began with a B.S. from Peking University, followed by M.S. and Ph.D. degrees from UCLA. Research Areas: Electronic Design Automation (EDA), Machine Learning Hardware, FPGA Prototyping, Optical Computing, Hardware Security, and CAD for Emerging Technologies Academic Timeline: Assistant Professor (2003-2008), Associate Professor (2008-2013), Full Professor (2013-present) His research focuses on design automation for mixed-signal circuits , GPU-accelerated EDA tools , and hardware-software co-design for AI . Recent work explores FFT-based optical neural networks and deobfuscation techniques for integrated circuits , reflecting his interdisciplinary approach at the intersection of machine learning , computer architecture , and semiconductor manufacturing . Key publication trends reveal expertise in: VLSI design , lithography optimization , and deep learning applications for EDA tools. His work has been recognized with multiple Best Paper Awards at top conferences including DAC , ASP-DAC , and HOST . Awards: IEEE Fellow (2014), SPIE Fellow (2017), ACM SRC Graduate Category Honors for students Patents: 8 U.S. Patents in electronic design and hardware optimization Prof. Pan has mentored 40 PhDs and postdocs who now hold key positions in academia and industry. He leads research initiatives involving GPU acceleration frameworks and optical computing architectures . His lab focuses on vertical integration of architecture, CAD tools, and fabrication technologies for next-generation hardware solutions.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Viktor Prasanna is the Charles Lee Powell Chair in Engineering and Professor of Electrical and Computer Engineering and Computer Science at the University of Southern California. He holds courtesy appointments in Computer Science and leads the Center for Energy Informatics, focusing on interdisciplinary research linking energy technologies, computer science, and engineering. Education: BE in Electronics (Bangalore University), ME (Indian Institute of Science), PhD in Computer Science (Pennsylvania State University) His research spans reconfigurable computing, FPGA accelerators, parallel and distributed systems, and big data applications. He has pioneered high-performance architectures and algorithms using FPGAs, impacting domains like networking, security, HPC, and machine learning. Prasanna has published over 600 papers, received 22 best paper awards, and secured >$50M in grants. His work emphasizes energy-efficient computing, with recent grants totaling $12.9M (2016–2021). His h-index is 73, with 23,454 total citations. Scientific Awards: IEEE Fellow, ACM Fellow, AAAS Fellow, W. Wallace McDowell Award, multiple Distinguished Alumnus Awards He has advised over 70 doctoral students and led major centers including CiSoft (Big Data in oilfield tech) and CAST. His editorial roles include Editor-in-Chief of IEEE Transactions on Computers and Journal of Parallel and Distributed Computing.
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Stephen Brown is a Professor at the University of Toronto within the Department of Electrical and Computer Engineering under the Faculty of Applied Science and Engineering. He earned his B.A.Sc and M.A.Sc in Electrical Engineering from the University of Toronto and New Brunswick, respectively, and a Ph.D. in Electrical Engineering from the University of Toronto (1992). His career spans over two decades in academia and industry collaboration. Education : B.A.Sc, University of New Brunswick M.A.Sc, University of Toronto Ph.D, University of Toronto Professor Brown’s research focuses on field-programmable gate arrays (FPGAs) , CAD algorithms , and computer architecture , with applications in machine learning and high-level synthesis . He is a principal investigator in the LegUp project , an open-source high-level synthesis framework that bridges software and hardware design. His work also extends to optimizing FPGA interconnect delays, physical synthesis, and logic block architectures. Key trends in his publications include advancements in high-level synthesis tools, FPGA architecture evaluation, and timing-driven design methodologies. His contributions often intersect with design automation , resource sharing , and embedded systems . Scientific Awards : NSERC 1992 Doctoral Prize Hart Professorship for Innovation in Teaching (2017) Multiple teaching excellence awards Best Paper Award at ICCAD 1990 Best Paper Award nomination at Canadian Conference on VLSI (1989) As Director of the FPGA University Program at Intel Corporation, he leads industry-academia initiatives. His teaching portfolio includes courses like ECE253 (Digital Logic) and ECE1733F (Switching Theory).
Mark C. Johnson is a Senior Lecturer at the Elmore Family School of Electrical and Computer Engineering at Purdue University, West Lafayette. He serves as Director of Instructional Laboratories and Associate Director for Design - Semiconductor Degree Program , overseeing laboratory infrastructure, CAD software administration, and curriculum development for courses like ECE337, ECE437, and ECE364. Education: Ph.D. in Electrical Engineering (1998), Purdue University M.S. in Electrical Engineering (1991), Wichita State University B.S. in Electrical Engineering (1983), Purdue University - Calumet His research focuses on electrical and computer engineering laboratory curriculum innovation , digital systems design , and CAD for VLSI . Over 15 recent publications highlight his work in SoC prototyping , low-power circuit design , and educational technology , spanning projects like FPGA filter optimization, dual-core processor experiments, and active learning strategies. Leadership Roles: Proceedings Chair (2003), MSE Program Chair (2005), MSE General Chair (2007), MSE Steering Committee Member, MSE & European Workshop on Microelectronics Education Chair, ECE Instructional Innovation Group (2004-2012) Secretary/Webmaster, ASEE Illinois/Indiana Section (2002-2011) He directs the ECE437 Computer Architecture Prototyping Lab and System on Chip Extension Technologies (SoCET) team , and co-advises the STARS semiconductor readiness program. Outside academia, he is an organist at Faith Presbyterian Church and composes keyboard music.
Albert H. Titus is a Professor in the Department of Biomedical Engineering and an Adjunct Professor in the Department of Electrical Engineering at the University at Buffalo, State University of New York. He serves as Associate Vice President for Regulatory Support in the Office of the Vice President for Research and Economic Development. His research focuses on analog VLSI design for neuromorphic visual processing, biosensors, wearable devices, optoelectronic systems, and neural networks. Education: PhD in Electrical and Computer Engineering, Georgia Institute of Technology (1997) MS in Electrical Engineering, University at Buffalo (1991) BS in Electrical Engineering, University at Buffalo (1989) Research Interests: His work spans wearable and implantable sensors, bioinstrumentation, neural network-based visual processing, analog VLSI implementations, optoelectronics, and electronic packaging. He pioneered CMOS-based neuromorphic systems and developed patented technologies for glare sensing and RF power calorimetry. Publication Trends: His recent articles emphasize CMOS-integrated sensors, machine learning for bioimpedance analysis, implantable medical devices, and xerogel-based optical biosensors. These works bridge biomedical engineering and microelectronics. Scientific Recognition: He is a Fellow of the National Academy of Inventors and has received the SUNY Chancellor’s Award for Excellence in Service (2017), NSF CAREER award, and Western New York Inventor of the Year (2010). His inventions include a patented low-power glare sensor (U.S. Patent 7,586,079) featured in Popular Science’s 2011 Top Ten Inventions. Academic Leadership: As a faculty member, he has supervised nearly 20 PhD and over 40 MS students, while teaching courses in circuits, IC design, sensors, and signal processing across electrical and biomedical engineering disciplines.
Professor Serdar Özoğuz is a full faculty member at the Department of Electronics and Communication Engineering , Istanbul Technical University . Holding a Ph.D. from ITU (2000) and a M.Sc. from ITU (1993) , he has taught courses like Active Network Synthesis , Basics of Electrical Circuits , and Scientific Research Ethics since 2014. His research focuses on Active RC filters Nonlinear electronic circuits Analog integrated circuit design Network synthesis . His recent publications emphasize machine learning applications in RF/microwave design , quantum computing for CAD tools , and emerging memory devices . The department's Devreler ve Sistemler Laboratuvarı Çok Geniş Ölçekli Tümdevre (VLSI) Tasarımı Laboratuvarı likely support his work. Despite no explicit awards listed, his 15+ recent articles in high-impact journals underscore his technical contributions.
Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.
Prof. Jörg Henkel serves as Professor and Head of the Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany. Previously a Senior Research Staff Member at NEC Laboratories Princeton, he holds a PhD from Braunschweig University (Summa cum Laude) and directs major research initiatives including the DFG's SPP 1500 program on 'Dependable Embedded Systems'. Research Focus: His work centers on embedded systems dependability , low-power design , and adaptive computing architectures . Through the SPP 1500 program and TR89 Collaborative Research Center, he pioneers fault-tolerance techniques and runtime adaptation for safety-critical applications, addressing energy efficiency challenges in hardware/software co-design. Scientific Recognition: IEEE Fellow (for contributions to low-power dependable embedded systems) Multiple Best Paper Awards (DATE 2008, ICCAD 2009, Codes+ISSS 2011/2014/2015) DAC 2014 Designer Track Best Poster Award DATE 2013 Best IP Award Leadership & Service: As Editor-in-Chief of IEEE Design&Test Magazine and former ACM TECS EiC, he shapes scholarly discourse. He has chaired premier conferences (ICCAD 2012/2013, ESWeek 2016) and delivered 10+ keynotes on embedded systems reliability. His DFG-coordinated projects secure substantial funding for national collaborative research. Technical Infrastructure: Leads the Chair for Embedded Systems (CES) within KIT's Institute of Technical Informatics, driving innovation in hardware/software co-design and invasive computing through the TR89 consortium.
