جست‌وجوی استاد و پژوهشگر

Eran Socherمشاهده پروفایل

استاد

• mm-wave CMOS circuit design
• THz sensing and imaging
• on-chip antennas
• +۳ مورد دیگر

Professor Eran Socher is a Full Professor at the School of Electrical Engineering, Tel Aviv University, where he heads the High Frequency Integrated Circuits and VLSI Labs. He has been a faculty member since October 2008 and previously served as a Visiting Professor at the University of Toronto (2015-2017). Professor Socher received his B.A. in physics (summa cum laude) and B.Sc., M.Sc., and Ph.D. degrees in Electrical Engineering from the Technion – Israel Institute of Technology. Prior to joining Tel Aviv University, he worked as a research engineer in the Israel Defense Forces (IDF) and as an adjunct lecturer at the Technion and Bar-Ilan University (2003-2006), followed by a position as a visiting researcher and assistant professor at UCLA (2006-2008). His research focuses on mm-wave CMOS circuit design for high-speed communications (>20Gbps) , THz sensing and imaging , and chip interfaces at these frequencies including on-chip antennas and waveguide transitions. Professor Socher has co-authored over 50 journal papers and 90 conference papers in prestigious venues including JSSC, T-MTT, MWCL, RFIC, IMS, SiRF and EuMIC. Analysis of his recent publications (2023-2025) reveals a strong focus on millimeter-wave and terahertz technologies, with particular emphasis on CMOS-based circuit design for communication systems, energy harvesting applications, and advanced antenna systems. His work spans frequencies from 5 GHz up to 0.6 THz, addressing challenges in power amplification, signal processing, and efficient RF-to-DC conversion. The research demonstrates consistent innovation in overcoming the limitations of silicon technology at extremely high frequencies. 2011 TAU Rector's Prize for Excellent Teaching 2015 TAU Rector's Prize for Excellent Teaching Professor Socher holds 8 patents in RF and mm-wave circuit design and regularly consults with industry on RFIC design and characterization. He leads the High Frequency Integrated Circuits and VLSI Labs at Tel Aviv University, where his team works on cutting-edge research in high-frequency integrated circuits. His laboratory focuses on developing CMOS solutions for next-generation communication systems, sensing applications, and imaging technologies that operate at millimeter-wave and terahertz frequencies.

• Computer Science
• Hardware Design
• Cryptography
• +۷ مورد دیگر

Dr. Yasir Ali Shah is a Lecturer in Computer Science at Ulster University's School of Computing, Engineering and the Built Environment , based at the Derry~Londonderry campus. His research focuses on hardware design, cryptography, and secure communication systems. Specialization: Post-Quantum Cryptography, Elliptic Curve Cryptography (ECC), FPGA/ASIC implementations Key Contributions: Optimization of cryptographic algorithms for IoT security, high-throughput hardware architectures Recent publications highlight advancements in post-quantum cryptography, including NTT/INTT optimizations, ECC hardware accelerators, and lightweight cipher implementations. His work spans both theoretical and applied domains, with a 2024 study on CPR efficacy indicating interdisciplinary collaborations. Selected trends in research output: 2024: 5 major papers on post-quantum crypto, IoT security, and medical applications 2023: Error-resistant NTT architectures and license plate recognition algorithms 2022: Optical interconnect designs and antiparasitic drug evaluations

• Analog and Digital Circuit Design
• Microelectronics
• Sensors
• +۳ مورد دیگر

Kyusun Choi is an Associate Professor in the Department of Computer Science and Engineering. His research focuses on analog and digital circuit design, microelectronics, and sensor technology, with expertise in ultrasonic transducers, thin film materials, and computer engineering. Recent publications highlight advancements in flexible thin-film PZT ultrasonic transducers, piezoelectric micromachined ultrasonic transducer (PMUT) arrays, and optimization frameworks for flash ADCs. These works emphasize thin film technology, finite element analysis, and dynamic programming approaches. His research aligns with the UN Sustainable Development Goals, particularly in Industry, Innovation, and Infrastructure. Collaborations include external institutions in areas like analog-to-digital converters, transducers, and comparator optimization algorithms.

Amit Acharyyaمشاهده پروفایل

استاد

• VLSI systems for resource-constrained applications
• Low-power design techniques
• Machine-learning hardware design
• +۱۴ مورد دیگر

Professor Amit Acharyya is a full Professor in the Department of Electrical Engineering at the Indian Institute of Technology Hyderabad, India. Previously he served as Associate Professor (2017–2022) and Assistant Professor (2012–2017) at the same institution, and earlier as Assistant Professor at IIT Guwahati and as Research Fellow at the University of Southampton, UK. He currently leads the AESICD Lab and is actively engaged in cutting-edge research spanning VLSI systems, low-power design, machine-learning hardware, biomedical devices, digital arithmetic, hardware security, and electric-vehicle battery monitoring. Education: PhD – University of Southampton, UK Research Interests: Professor Acharyya’s work centers on the design of resource-constrained VLSI systems with emphasis on ultra-low power techniques, hardware accelerators for machine learning, and edge-computing solutions. His group is developing application-specific chips for remote health monitoring targeting cardiovascular diseases, diabetes, autism spectrum disorder, neurological disorders, and orthopaedic challenges. Additional thrust areas include hardware–software co-design for accelerated cancer diagnostics, efficient digital arithmetic circuits, hardware security primitives, real-time battery-health monitoring for electric vehicles, and nanomagnetic logic systems. Scientific Awards & Recognition: Digital Trail Blazer Award, Digital Technology Conclave 2016 Visvesvaraya Young Faculty Fellowship 2015–16 Young Engineer Award, IEI 2015 Visiting Research Fellowships, University of Southampton (2015–2017) & Newcastle University (2016–2017) Summer Fellowship, University of Liverpool 2015 Advising & Funding: He has mentored 15 current PhD scholars and 13 graduated students, many funded by DST, government R&D labs, and industry partners. Research projects span VLSI DSP, IoT for healthcare, structural health monitoring, AI-based fault-tolerant IC design, hardware security, and battery-management systems. Research Laboratory: He heads the Application-Specific Integrated Circuits & Devices (AESICD) Laboratory at IIT Hyderabad, which focuses on developing next-generation low-power SoCs and domain-specific accelerators.

Ashudeb Duttaمشاهده پروفایل

استاد

• Analog Circuit Design
• Radio Frequency (RF) VLSI Chip Design
• Receiver Phase Locked Loop
• +۴ مورد دیگر

Ashudeb Dutta is a Professor in the Department of Electrical Engineering at the Indian Institute of Technology Hyderabad. His research focuses on analog and RF VLSI chip design, including applications in wireless communication systems and semiconductor devices. Education: Ph.D. from Indian Institute of Technology Kharagpur Research Interests: Analog and RF VLSI chip design, Receiver Phase Locked Loop, Low Noise Amplifier, Energy Harvesting, Semiconducting Devices, and Wireless Communication & Networks. Contact Information: Office: Room C-403, Academic Block C, IIT Hyderabad, Kandi-502284, Sangareddy, Telangana, India Email: ashudeb.dutta@iith.ac.in Phone: (040) 2301 - 6453

Rajesh Kediaمشاهده پروفایل

استادیار

• Computer Architecture
• Embedded Systems
• VLSI Design Automation
• +۶ مورد دیگر

Rajesh Kedia is an Assistant Professor in the Department of Computer Science & Engineering at Indian Institute of Technology Hyderabad . He received his Ph.D. from IIT Delhi under the supervision of Prof. M. Balakrishnan and Prof. Kolin Paul, and holds a B.Tech. in Electronics and Communication Engineering from MNIT Jaipur (2006). His research focuses on computer architecture , embedded systems , and VLSI design automation , with specific emphasis on thermal management of processors and memories , shared resource management , and FPGA-based accelerator design . His recent publications address CNN execution time prediction, thermal modeling for 3D systems, and efficient resource allocation in multi-accelerator environments. Rajesh has received multiple scientific awards including the Visvesvaraya Ph.D. fellowship , IEEE Senior Member designation, and a BEST PAPER NOMINATION at DATE 2022 . He has mentored several Ph.D. and M.Tech students, including Lakshay Arora , Venugopal Ramamurthy , and M A Muneeb , with research topics spanning compilers, thermal management, and RISC-V architecture. He actively contributes to the academic community as a reviewer for leading conferences/journals (ASPDAC, DAC, IEEE ESL, CODES+ISSS) and previously served as Design Contest co-chair for ISLPED 2024 . His work has been supported by a SERB startup research grant (INR 20.26L) for shared resource management research.

Sobhan Babuمشاهده پروفایل

دانشیار

• Big Data Analytics
• Graph Theory
• Algorithms
• +۴ مورد دیگر

Dr. Sobhan Babu is an Associate Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Hyderabad (IIT Hyderabad). His research focuses on Big Data Analytics, Graph Theory, Algorithms, and Applied Machine Learning. He obtained his Ph.D. and MTech from IIT Bombay, and his BE from the University of Madras. Education Ph.D. in Computer Science, IIT Bombay MTech in Computer Science, IIT Bombay BE in Computer Science, University of Madras Diploma in Computer Engineering, AANM&VVRSR Polytechnic Research Interests His work bridges theoretical and applied Computer Science. In Graph Theory, he investigates structural graph properties, subdivisions, and directed graph algorithms. In AI/ML, he explores optimization techniques for VLSI design and power-efficient testing. His Big Data Analytics focus includes developing algorithms for efficient data processing and modeling. Publications His publications span VLSI optimization, algorithmic game theory, and graph theory. Key themes include power minimization in scan testing, market equilibrium algorithms, and graph structural conditions. Recent accepted works extend existing research on cycles and unicyclic graphs, indicating sustained theoretical contributions. Contact Email: sobhan@iith.ac.in Office: Room CS-307, Computer Science Building, IIT Hyderabad, Telangana, India.

Anand Raghunathanمشاهده پروفایل

استاد

• Brain-inspired Computing
• Machine Learning
• System-on-Chip Design
• +۷ مورد دیگر

Anand Raghunathan is a Silicon Valley Professor and Chair of the VLSI area at Purdue University's Elmore Family School of Electrical and Computer Engineering. He serves as Associate Director of the $36M SRC/DARPA Center for Brain-inspired Computing (C-BRIC) and Co-Director of the Purdue/TSMC Center for a Secure Microelectronics Ecosystem (CSME). His research focuses on Brain-inspired computing Energy-efficient machine learning System-on-chip design Post-CMOS devices Heterogeneous computing Educated with a B.Tech from IIT Madras, and MA/PhD in Electrical Engineering from Princeton University, he directs Purdue's Integrated Systems Laboratory (ISL) which explores domain-specific architectures and compute-in-memory technologies. His work spans security for embedded systems, battery-efficient computing, and computational imaging commercialized through High Performance Imaging, Inc. Research keywords include: Neural network acceleration Hardware-software co-design Security vulnerabilities Post-CMOS devices Transformer optimization Scientific awards include: IEEE Fellow MIT TR35 innovator 9 Best Paper Awards 2 NEC Technology Commercialization Awards Purdue Faculty Excellence Award Advising and grants: Co-founded High Performance Imaging, Inc. Founded Purdue/TSMC Center for Secured Microelectronics Ecosystem Hold 29 U.S. and 16 international patents Chair of 5 IEEE/ACM conferences Editorial roles in ACM/IEEE journals Labs and teams: Integrated Systems Laboratory (ISL) Collaborations with NEC Labs, Princeton University, and IIT Madras Lead $36M SRC/DARPA C-BRIC Center

Jae-sun Seoمشاهده پروفایل

استادیار

• Machine Learning
• Neuromorphic Algorithms
• Integrated Power Management
• +۵ مورد دیگر

Jae-sun Seo is an Assistant Professor at Arizona State University's School of Electrical, Computer and Energy Engineering (ASU), joining in 2014. He previously worked at IBM T. J. Watson Research Center (2010-2013) and held internships at Intel and Sun Microsystems during his graduate studies. His research focuses on machine learning hardware , neuromorphic algorithms , and power management , with expertise in FPGA acceleration and VLSI design. Key research themes: Hardware acceleration of deep learning via FPGAs Neuromorphic computing with CMOS and resistive devices Energy-efficient integrated circuits for AI Power management techniques in high-performance processors His awards include the Samsung Scholarship (2004-2009), IBM Technical Achievement Award (2012), and NSF CAREER Award (2017). He has served on program committees for ISLPED, ISOCC, and ICCD, and reviewed for ISCAS.

• Life and Health Informatics
• Computer Systems
• Control and System Engineering
• +۵ مورد دیگر

Masao Yanagisawa is a Professor at Waseda University's School of Fundamental Science and Engineering, with over 25 years of academic experience since 1998. An IEEE and ACM member, he holds a Doctor of Engineering degree from Waseda University.

• Analog Integrated Circuits
• Mixed-Signal VLSI Design
• High-Speed Data Converters
• +۷ مورد دیگر

Yan Zhu is a faculty member at the University of Macau , affiliated with the Analog and Mixed Signal VLSI Laboratory within the Faculty of Science and Technology. She has a strong research focus on high-performance analog and mixed-signal integrated circuits, particularly in data conversion and low-power design. Her research interests include: Analog and Mixed-Signal VLSI Design High-Speed Data Converters (ADCs) Noise-Shaping and Time-Domain Circuits PVT-Robust and Low-Power Circuit Techniques Compute-in-Memory and AI Hardware Acceleration The recent publications of Yan Zhu demonstrate a clear trend toward advanced ADC architectures such as time-interleaved, pipelined-SAR, and time-domain converters, with a strong emphasis on calibration, linearity, and energy efficiency. Her work frequently appears in top-tier journals like IEEE JSSC and conferences like ISSCC and CICC, indicating leadership in the field of analog circuit design. There is also a growing focus on machine learning hardware, particularly analog compute-in-memory systems for edge AI applications. No scientific awards or honors are mentioned in the provided text. Yan Zhu has made significant contributions through collaborative research, particularly with Chi-Hang Chan and Rui Paulo Martins , and has been involved in numerous projects related to ADC calibration, metastability, and high-speed sampling. While specific grant details are not listed, the volume and quality of publications suggest active funding support. She has not listed any advisees in the provided data. She is a core contributor to the Analog and Mixed Signal VLSI Laboratory at the University of Macau, where her team focuses on cutting-edge IC design for communication, sensing, and artificial intelligence applications.

Alex Orailogluمشاهده پروفایل

استاد

• Electronic Design Automation
• VLSI Test
• Fault-Tolerant ICs
• +۳ مورد دیگر

Alex Orailoglu is a Professor at the Department of Computer Science and Engineering (CSE) at the University of California, San Diego (UCSD), since 1987. He leads the Reliable System Synthesis Group and specializes in Electronic Design Automation, VLSI Test, and Synthesis of Fault-Tolerant ICs. His work has produced over 80 publications and has advised 6 Ph.D. and 2 M.S. students. Education: S.B. in Applied Mathematics (Harvard University, 1977) M.S. in Computer Science (University of Illinois, Urbana, 1979) Ph.D. in Computer Science (University of Illinois, Urbana, 1983) Research focuses on hardware security, VLSI testing, and neural network robustness. His recent work includes logic obfuscation techniques to counter reverse engineering and methods for enhancing DNN fault tolerance. Professional involvement includes roles as General Chair, Program Chair, and Steering Committee member for conferences like IEEE VLSI Test Symposium and High-Level Design Validation Workshops. He has secured funding from the National Science Foundation, Intel, and other industry partners. Advising & Grants: Current advising includes 6 Ph.D. and 2 M.S. students. Notable sponsored research includes collaborations with NASA, NATO, and major tech firms like Agilent and Hewlett-Packard. Labs: Directs the Reliable System Synthesis Group (RSS Group) at UCSD, focusing on secure hardware design and embedded systems.

Grzegorz Blakiewiczمشاهده پروفایل

دانشیار

• Microelectronics
• Electronic Systems
• Integrated Circuits
• +۳ مورد دیگر

Grzegorz Blakiewicz serves as an Associate Professor at the Department of Microelectronic Systems within the Faculty of Electronics, Telecommunications and Informatics at Gdańsk University of Technology, where he maintains an active academic position in Building A of the faculty complex. His research expertise spans core areas of Microelectronics with specialized focus on: Integrated Circuit Design VLSI Architecture Semiconductor Device Physics Embedded System Development Microelectronic System Optimization Telecommunications Hardware Implementation Contact is available via institutional email at grzblaki@pg.edu.pl .

Krystyna Dziubichمشاهده پروفایل

مدرس ارشد

• Computer Architecture
• Embedded Systems
• Digital Systems Design
• +۳ مورد دیگر

Krystyna Dziubich serves as a Senior Lecturer in the Department of Computer Systems Architecture at the Faculty of Electronics, Telecommunications and Informatics, Gdańsk University of Technology. Her office is located in Building A of the Faculty, with contactable via email (krydziub@pg.edu.pl) and telephone (583472389). Her research spans critical domains of modern computing hardware development: Computer Architecture Embedded Systems Digital Systems Design Hardware Security Reconfigurable Computing VLSI Design These research areas address fundamental challenges in creating efficient, secure, and adaptable computing systems for contemporary technological demands. Her work contributes to advancements in processor design, hardware acceleration, and security mechanisms for specialized computing environments. While specific publications and projects aren't detailed in the available information, her departmental affiliation indicates active engagement in both teaching and research within computer engineering disciplines.

Izzet Kaleمشاهده پروفایل

استاد

• Digital Signal Processing
• Analogue Signal Processing
• Mixed-Signal Circuit Design
• +۷ مورد دیگر

Professor Izzet Kale serves as the Head of the Department of Engineering at the University of Westminster and Director of the Applied DSP and VLSI Research Group, which he founded in the late 1980s. His leadership spans academic administration, cutting-edge research, and extensive industry collaboration with European, US, and Japanese corporations. Professor Kale's research portfolio is exceptionally diverse, spanning digital and analogue signal processing, mixed-signal silicon circuit design (both synchronous and asynchronous), sensor networks, GNSS receivers, biomedical signal processing, satellite on-board processing, and communication systems. His current research focuses on low-power DSP algorithms and devices applicable across communications, GNSS, sensors, and biomedical industries, with particular emphasis on Internet of Things applications. He leads innovative work in sensor networks for ground monitoring, UAV-based environmental sensing, and wearable health devices, while collaborating with the European Space Agency on efficient low-power reconfigurable channeliser algorithms for next-generation satellite systems. His publication record demonstrates remarkable consistency and impact across multiple domains, with research trending toward increasingly integrated solutions that bridge hardware design, signal processing algorithms, and real-world applications in healthcare, environmental monitoring, and satellite communications. Recent work shows particular strength in biomedical signal processing (especially ECG analysis), secure low-power circuit design, and advanced GNSS interference mitigation techniques. Professor Kale has served extensively in professional capacities including IEEE UK&I Section Committee membership for multiple years and currently serves as Chapter Chair for the CAS and I&M Chapters. He has contributed significantly as Associate Editor, Reviewer, and Special Session Organizer for IEEE and RIN journals, while maintaining a 100% track record in successful delivery of industry-sponsored research contracts. His academic mentorship has been substantial with 31 PhD students successfully graduated and 7 currently under supervision. His research has been supported by diverse funding sources including Sabancı University Nanotechnology Research Center, Defence and Security Accelerator, European Commission, British Council, and European Space Agency, reflecting the broad applicability and impact of his work across multiple sectors. The Applied DSP and VLSI Research Group under his leadership has established itself as a center of excellence for next-generation product-oriented applied research, consistently translating theoretical advances into practical implementations through strong industry partnerships and interdisciplinary collaboration.