Stephen W. Keckler is an Adjunct Professor at the Department of Computer Science , The University of Texas at Austin , and serves as Vice President of Architecture Research at NVIDIA . He is an ACM Fellow , IEEE Fellow , and Sloan Foundation Research Fellow . Education: BS in Electrical Engineering, Stanford University (1990) SM in Computer Science, Massachusetts Institute of Technology (1992) PhD in Computer Science, MIT (1998) Research Interests focus on computer architecture for deep learning , GPU computing , and energy-efficient systems . His work explores memory compression , network-on-chip designs , and heterogeneous computing . Publication Trends highlight advancements in deep learning accelerators , GPU memory systems , and energy-efficient architectures . Notable themes include sparsity exploitation , multi-chip modules , and fault-tolerant GPU pipelines . Scientific Recognition : ACM Fellow IEEE Fellow Sloan Foundation Research Fellow Best Paper Awards at ASPLOS 2009 and ISPASS 2011 Laboratory Affiliations : Computer Architecture and Technology Laboratory (CART) TRIPS Project (Tera-Op Reliable Intelligently adaptive Processing System) NVIDIA Research
Aviral Shrivastava is a Professor at the School of Computing and Augmented Intelligence, Arizona State University, leading the Make Programming Simple Lab. He holds a Ph.D. and M.S. from the University of California-Irvine (2006, 2002) and a Bachelor’s from IIT Delhi (1999). His research focuses on making programming simple for embedded and cyber-physical systems, with a particular interest in manycore and accelerated computing, software for CPS, and resilient/fault-tolerant computing. He has co-authored over 120 publications in top venues like DAC, ESWEEK, and ACM TECS, with more than 3000 citations and 5 granted patents. His work has been recognized with multiple awards, including the 2010 NSF CAREER award and best paper nominations. Research Areas: Embedded and Cyber-Physical Systems Compiler Design for Modern Architectures Resilient and Fault-Tolerant Computing Scientific Awards: 2010 NSF CAREER award DAC 2017 Best Paper Award Candidate VLSI 2016 Best Student Paper Award LCTES 2010 Second Highest Ranked Paper ASPDAC 2008 Best Paper Candidate Advising & Grants: He has mentored 9 Ph.D. and over 20 Masters students. His research has been funded by NSF, DOE, NIST, SFAZ, and industry partners, totaling $3.5M. He teaches courses on computer organization, architecture, and embedded systems, with student evaluations averaging over 4/5. He also serves as General Chair of Embedded Systems Week (ESWEEK) and holds editorial roles in IEEE ESL, ACM TCPS, and ACM TECS.
Nicola Nicolici is a Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on methods and algorithms for the design of digital integrated circuits and systems, with significant contributions in manufacturing test, post-silicon validation and debug. His work has expanded to include embedded systems, low-energy computing, and custom hardware-accelerated computing systems. Professor Nicolici's research interests span multiple areas of digital system design and validation. His early work focused on manufacturing test methodologies and power-aware testing strategies for integrated circuits. More recently, he has made significant contributions to post-silicon validation techniques, including constrained-random stimuli generation, trace signal selection, and bit-flip detection. His research has evolved to address emerging challenges in embedded computing systems, low-energy design, and specialized hardware acceleration for various applications including deep neural networks and signal processing. His recent publications reveal a strong trend toward hardware acceleration for specialized computing tasks. The research spans matrix multiplication algorithms (Strassen and Karatsuba), memory system optimization (DDR5 calibration), FPGA-based radar processing, and neural network acceleration. His work consistently bridges theoretical algorithm development with practical hardware implementation considerations, particularly focusing on precision analysis, fault tolerance, and energy efficiency. The research demonstrates a clear progression from traditional digital circuit testing to more complex system-level validation and acceleration techniques. Professor Nicolici has been actively involved in teaching courses related to system-on-chip design and test, digital systems, and embedded systems. His teaching portfolio includes advanced courses such as System-on-Chip (SOC) Design and Test and Digital Systems Design , reflecting his expertise in the field. While specific grant information isn't detailed in the provided text, his extensive publication record suggests ongoing research funding support. His research has contributed significantly to the fields of digital circuit testing, post-silicon validation, and hardware acceleration. The work has practical applications in semiconductor manufacturing, embedded systems design, and specialized computing architectures. His recent focus on neural network acceleration and memory system optimization reflects the evolving landscape of computer architecture research.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Prof. Dr.-Ing. Jürgen Teich is a full Professor and Chair for Hardware-Software Co-Design at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU). He serves as Head of Department Computer Science and Vice Dean of the Technical Faculty since August 2024, and has been Speaker of the FAU Research Center Embedded System Initiative (FAU ESI) since 2023. His educational background includes: Diploma degree in Electrical Engineering, University of Kaiserslautern (1989) Dr.-Ing. degree in Electrical Engineering, University of Saarland (1993) Habilitation (PD Dr.-Ing.) entitled "Synthesis and Optimization of Digital Hardware/Software Systems" (1996) Prof. Teich's research focuses on Embedded Systems , Invasive Computing , Hardware-Software Co-Design , and Reconfigurable Computing . His work spans from theoretical foundations to practical implementations, with particular emphasis on resource-constrained systems, many-core architectures, and energy-efficient computing. He has pioneered research in invasive computing paradigms that enable more efficient use of many-core processors by allowing applications to dynamically claim resources. His recent publications reveal a strong trend toward energy-efficient AI deployment on embedded devices , security of embedded systems , and novel memory technologies . There's a clear focus on practical implementations of machine learning on microcontrollers (TinyML), hardware acceleration for data processing, and innovative approaches to power management in self-powered systems. Among his notable scientific awards are: IEEE Fellow (since 2018) Member of Academia Europaea, Section Informatics (since 2011) Member of the National Academy of Science and Engineering (acatech) (since 2018) Member of the German Society of Humboldtians (since 2021) Prof. Teich has been Principal Investigator for numerous DFG-funded projects including SFB/Transregio 89 "Invasive Computing" (2010-2022), SFB 694, and multiple priority programs. He has coordinated large collaborative research efforts across Germany and internationally, with significant funding from DFG and other sources. His research group has produced influential work in embedded systems design and co-design methodologies. He leads the Hardware-Software Co-Design research group at FAU, which focuses on innovative approaches to embedded system design, invasive computing architectures, and efficient implementation of machine learning on resource-constrained devices. The group maintains strong collaborations with industry partners including Intel, Xilinx, and automotive companies.
Tsun-Ming Tseng is a Professor and principal investigator at the Chair of Electronic Design Automation at the Technical University of Munich (TUM). He leads the Emerging Technology Group and oversees multiple DFG/BMBF-funded research projects in the areas of microfluidic large-scale integration, optical network-on-chip design, and novel microfabrication techniques. Dr. Tseng's research focuses on design automation for emerging technologies, with particular expertise in three main areas: microfluidic large-scale integration, optical network-on-chip systems, and novel microfabrication processes. His work bridges the gap between electronic design automation and cutting-edge applications in bioengineering, photonics, and advanced manufacturing. His research group develops sophisticated algorithms and tools for optimizing design, reliability, and performance in these emerging domains. Analysis of Dr. Tseng's recent publications reveals a strong focus on practical implementation challenges in emerging technologies. His work spans both theoretical algorithm development and practical system implementation, with particular emphasis on reliability, performance optimization, and manufacturing considerations. The research shows increasing integration between different technology domains, particularly the convergence of microfluidics, optical networking, and electronic design automation. Dr. Tseng has been awarded multiple significant research grants including: "DE-TW-CloudWRONoC" (BMBF-NSTC project, PI, 2025-2028, EUR 797.7K) "DE-TW-PI3D" (BMBF-NSTC project, PI, 2024-2027, EUR 391.6K) "Physical Design for Microfluidic Large-Scale Integration" (DFG research grant, PI, 2024-2026, EUR 331.9K) Multiple other DFG and industrial projects totaling over EUR 3 million in funding He has successfully supervised numerous doctoral researchers and postdoctoral fellows, with current group members including Jiahui Peng, Debraj Kundu, Liaoyuan Cheng, and several others. Dr. Tseng leads the Emerging Technology Group at TUM, which focuses on developing design automation methodologies for next-generation technologies. The group maintains strong collaborations with international institutions, including partnerships with researchers in Taiwan and Hong Kong. The team operates state-of-the-art facilities for research in microfluidics, optical networking, and advanced microfabrication techniques.
Zhidan Zheng is a researcher at the Technical University of Munich (TUM), working within the Chair of Electronic Design Automation led by Prof. Ulf Schlichtmann. His office is located in room 0509.05.911 at Arcisstr. 21, 80333 Munich, with direct contact available via email zhidan.zheng@tum.de and phone +49 (89) 289 - 23692. Zheng holds a Master of Science degree as indicated by his academic title M.Sc. and has been actively contributing to the field of optical interconnects and network-on-chip design. Zheng's research focuses on wavelength-routed optical networks-on-chip, with particular expertise in network topology optimization, fault tolerance mechanisms, waveguide routing algorithms, and bandwidth allocation strategies. His work addresses critical challenges in photonic integrated circuit design, including thermal variation effects, crosstalk mitigation, and lifetime extension for communication-intensive systems. Zheng has developed several innovative methodologies including ToPro+ for topology projection, LightR for fault-tolerant architectures, and WROXIM for network-level simulation. Analysis of Zheng's publication trends from 2021-2025 reveals a consistent focus on practical implementation challenges of optical networks-on-chip. His research has evolved from foundational topology design (Light, 2021) to increasingly sophisticated solutions addressing reliability (LightR, 2023) and comprehensive system integration (ToPro+, 2025). The work demonstrates strong collaboration with researchers including Mengchu Li, Tsun-Ming Tseng, and Ulf Schlichtmann across multiple high-impact venues including DAC, DATE, ICCAD, and ASP-DAC. Zheng actively contributes to the Electronic Design Automation research group at TUM, participating in projects related to analog EDA, emerging technologies, and optical networks. His research is situated within TUM's broader initiatives in photonic integration and high-performance computing architectures, working closely with Prof. Schlichtmann's team on funded projects in the optical NoC domain.
Wenfeng Zhao is an Assistant Professor in the Department of Electrical and Computer Engineering at Binghamton University. He holds a PhD from the National University of Singapore (2014) and BS/MS degrees from Huazhong University of Science and Technology (2007-2009). Prior to this role, he conducted postdoctoral research at the University of Minnesota's Biomedical Engineering Department. His research focuses on neural engineering, compressed sensing, ultra-low-power VLSI systems, and in-memory computing. Key areas include hardware security, biomedical signal processing, and energy-efficient computing architectures. His work spans applications in neural interfaces, cryptographic hardware, and IoT edge devices. Recent publications highlight advancements in block-cipher-in-memory architectures, emotion recognition via EEG analysis, and energy-efficient FPGA accelerators for neural networks. His research also addresses challenges in cryogenic memory systems and MRI-compatible neural recording devices. Zhao's contributions emphasize interdisciplinary approaches at the intersection of hardware design, signal processing, and cybersecurity. His lab develops novel solutions for low-power embedded systems and trustworthy IoT infrastructure.
Stefan Hougardy is a Professor at the Research Institute for Discrete Mathematics, part of the Mathematisch-Naturwissenschaftliche Fakultät at the University of Bonn. He is actively engaged in research and teaching, with a focus on discrete mathematics and combinatorial optimization. He contributes to academic governance through roles in examination boards, teaching mentoring, and faculty committees. Stefan Hougardy's research lies at the intersection of theoretical computer science and practical optimization. His primary interests include approximation algorithms, the Traveling Salesman Problem (TSP), Steiner trees, graph theory, and VLSI design automation. He develops efficient algorithms for NP-hard problems and analyzes their theoretical performance guarantees. His work often bridges theory and application, particularly in electronic design automation and mathematical programming. His recent publications demonstrate a strong focus on the complexity and approximation of combinatorial optimization problems. Key themes include the analysis of local search heuristics like k-opt for TSP, edge elimination techniques, fast matching algorithms, and optimal legalization in chip design. His work combines rigorous theoretical analysis with practical implementation and computational experiments. MPC 'Outstanding Paper of the Year' Award 2024 Stefan Hougardy supervises graduate students and leads seminars on discrete mathematics and optimization. He is involved in the Bonn International Graduate School of Mathematics and the Hausdorff Center for Mathematics, contributing to doctoral education and mentoring. While specific grant details are not listed, his sustained research output and leadership roles suggest active funding support. He also contributes to curriculum development and academic quality assurance through various institutional committees. He is affiliated with the Research Institute for Discrete Mathematics at the University of Bonn, a leading center for combinatorial optimization and algorithmic research. The institute is closely linked with the Hausdorff Center for Mathematics, fostering collaboration in discrete and applied mathematics.
Fabrizio Lombardi is the ITC Endowed Professor at Northeastern University's Department of Electrical and Computer Engineering, part of the College of Engineering. He previously held faculty positions at Texas Tech University, University of Colorado-Boulder, and Texas A&M University. He earned his B.Sc. from the University of Essex (1977), M.Sc. and Ph.D. from the University of London (1982). His research focuses on fault-tolerant computing, VLSI CAD, quantum computing, and configurable computing systems. He has led major projects like the NSF-funded Neural-Network-based Stochastic Computing Architectures for Machine Learning . He holds leadership roles including President of the IEEE Nanotechnology Council (2022-2023), IEEE Computer Society Vice President (2021), and IEEE PSPB member. His 200+ publications span IEEE Transactions on Computers, Nanotechnology, and Design & Test. Awards include IEEE Fellow, Søren Buus Outstanding Research Award, and multiple research fellowships. His work bridges theory and application, emphasizing defect-tolerant nanosystems and energy-efficient computing hardware. Recent innovations include approximate computing methodologies and secure PUF-based hardware designs.
Carl-Mikael Zetterling is a Professor and Head of Department at Kungliga Tekniska Högskolan (KTH) in Stockholm, Sweden, affiliated with the School of Electrical Engineering and Computer Science (ICT) and the Electronics and Embedded Systems department. His research focuses on process technology and device design for high-temperature, high-power silicon carbide (SiC) electronics, expanding into SiC-based analog and integrated circuits. He has authored over 300 publications, including books on SiC process technology and plagiarism prevention. Dr. Zetterling has held leadership roles such as Vice Dean of the School of ICT (2013–2017) and teacher representative on KTH's faculty board. He has collaborated internationally at Stanford University, Kyoto University, and Kyoto Institute of Technology. His work addresses applications in extreme environments, including Venus exploration and fusion reactor monitoring, with a focus on radiation tolerance and thermal resilience. The 15 most recent publications highlight trends in wide bandgap semiconductors, gamma irradiation effects on SiC devices, and high-temperature integrated circuits. His articles span structural health monitoring with machine learning, novel SiC diode designs, and radiation-hardened electronics. Key contributions include advancements in self-aligned contacts, trench MOSFETs, and compact modeling for extreme conditions. While no formal awards are listed, his roles in technical program committees (TMS Electronic Materials Conference, IEEE SISC Conference) and editorial work demonstrate significant academic service. He teaches courses ranging from digital design to high-temperature electronics, overseeing degree projects in embedded systems, communication, and nanotechnology.
Sule Ozev is a Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU). She holds a Ph.D. in Computer Science and Engineering from the University of California, San Diego (2002), and has been a faculty member since 2008. Her research focuses on analog and mixed-signal circuit testing, fault-tolerant systems, and RF circuit reliability. She has published over 100 papers and holds a U.S. patent. Notable awards include the NSF CAREER Award (2006) and the ASU Joseph Palais Distinguished Faculty Scholar Award (2023-2024). Her education includes: Ph.D., Computer Science and Engineering, UC San Diego (2002) M.S., Computer Science and Engineering, UC San Diego (1998) B.S., Electrical Engineering, Bogazici University, Turkey (1995) Research Interests: Self-test and calibration techniques for analog/RF circuits, fault simulation, and reliability enhancement. Recent work includes BIST solutions for power management units, MEMS sensor calibration, and IoT security. Publications span RF impedance measurement, low-power systems, and marine sensor applications. Awards also include best paper recognitions at IEEE VLSI Test Symposium (2022) and European Test Symposium (2019). Grants include NSF-funded projects on adaptive test strategies and collaborative research on sensor networks. Service roles include associate editor for IEEE Transactions on VLSI Systems and program chairs for major conferences.
Dr. Patrick W. C. Ho is a Lecturer in the Department of Electrical & Computer Systems Engineering (ECSE) at Monash University Malaysia School of Engineering. He holds a PhD in Electronics Engineering from the University of Nottingham Malaysia Campus (2016), with research focusing on non-volatile FPGA architectures using memristors. His academic journey includes roles as a Scholarly Teaching Fellow and unit coordinator for courses like ECE2131 Electrical Circuits and ECE4063 Large Scale Digital Design. He has industry experience with Intel Microelectronics and Altera Corporation, alongside teaching A-level Physics at Methodist College Kuala Lumpur. Education: BEng (First Class Honours) in Engineering (2009) MSc in Science (2012) PhD in Electronics Engineering (2016) Research Interests: Dr. Ho specializes in memristor-based non-volatile memory systems, VLSI design, and FPGA architectures. His work bridges hardware design with emerging materials, as seen in his Q1 journal article on memristive LUTs. Collaborations with CAD-IT expand his focus into AI, image processing, and object recognition. Recent projects include studies on memristor substrate performance (2023–2026) and UAV communication reliability (2021–2024). Teaching and Industry Engagement: As ECSE’s Industrial Training Advisor and IAP representative, he actively connects academic curricula with industry needs. His teaching spans foundational engineering courses and advanced digital design modules. Labs and Collaborations: Active in CAD-IT partnerships for student FYP co-sponsorship. Research groups focus on nanotechnology, machine learning integration in UAV systems, and memristor material analysis.
Luca Sterpone is a Full Professor at the Department of Control and Computer Science (DAUIN), Politecnico di Torino. He serves as Head of the Control and Computer Engineering Department (2023-2027), coordinates the Aerospace and Safety Computing Lab, and is a member of the Academic Senate and Power Electronics Innovation Center (PEIC). His research spans reconfigurable computing, fault tolerance, and radiation effects analysis in electronic systems. Professor since 2021 Department Head (DAUIN) since 2023 Coordinates international collaborations with ESA, AMD Xilinx, NVIDIA, and Thales Alenia Space Develops radiation-hardened FPGA tools (SETA, VERI-Place, PyXEL) 2007 EDAA Outstanding Dissertation Award and 2005 IEEE Best Paper Award Research Focus : Designing radiation-tolerant systems for aerospace, including fault-tolerant AI accelerators, FPGA reliability, and software-based error mitigation. He investigates soft error propagation in nanoscale circuits and develops tools for radiation sensitivity analysis in VLSI. His work integrates hardware-software co-design for mission-critical applications. Awards : EDAA Outstanding Dissertation Award (2007) IEEE European Test Symposium Best Paper (2005) SMACD Best EDA Tool Award (2018) ARC Best Paper candidate (2018) Teaching : He leads courses in Reconfigurable Computing (PhD level), GPU Programming , and Operating Systems . He has formal responsibility for teaching roles across 9 bachelor's and 7 master's years, and mentors multiple PhD students. Collaborations : Coordinates with the European Space Agency (ESA), University of Bielefeld, Universidad de Sevilla, and industrial partners like AMD Xilinx, NVIDIA, and General Motors. He leads projects such as RESCHIP4EU, VEGAS, and TERRAC for radiation-hardened computing solutions.
