Aurèle Maheo is a Research Fellow at the Computer Science Department of Telecom SudParis, affiliated with the Parallel and Distributed Systems (PDS) group. His research focuses on distributed systems, parallel computing, and hardware acceleration, with applications in machine learning and high-performance computing. He has contributed to projects such as SpeedyLoader for optimizing machine learning pipelines and FPGA memory bandwidth improvements. His work bridges theoretical distributed systems principles with practical implementation challenges in large-scale environments. Affiliations: PDS Group, Computer Science Department, Telecom SudParis Research interests include distributed consensus algorithms, system scalability, and hardware-software co-design for accelerating computational workflows. Recent work highlights include presentations on machine learning pipelining techniques and FPGA-based memory optimization strategies.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and Deputy Director and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research & Technology - Hellas (FORTH). He co-founded the European Research Center on Computer Architecture (EuReCCA) and is a founding partner of the European Network of Excellence on High-Performance and Embedded Architecture and Compilation (HiPEAC). PhD in Computer Science from University of California, Berkeley (1983) Co-founder of EuReCCA (2011) Contributed to RISC architecture (1980-1983), interconnection networks (1985-2011), and parallel computing (1993-2010) His research spans Scalable Multicore Systems , Interconnection Network Architecture , Packet Switch Design , Computer Architecture , and VLSI Systems . He has made foundational contributions to per-flow queueing, backpressure mechanisms, and wormhole IP over ATM, with applications in internet routers, data centers, and supercomputers. His publications focus on high-radix crossbar switches, flow control algorithms, and explicit interprocessor communication. Notable scientific awards include: ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981-1983) Greek State Fellowship (1973-1978) He has supervised 40 graduate theses and participated in 22 R&D projects totaling €9M, including HiPEAC (coordinator of interconnection networks), SARC (FPGA prototype design), and ENCORE (cache-optimized remote DMA). His work has received over 2000 citations, with an h-index of 23.
Giovanna Turvani is an Associate Professor at the Department of Electronics and Telecommunications (DET) at Politecnico di Torino, with affiliations in both the College of Electronic, Telecommunications and Physics Engineering and the College of Computer, Film, and Mechatronics Engineering. Scientific Branch: IINF-01/A - Electronics ERC Sectors: PE7_4, PE7_11, PE6_1, PE6_14, PE7_3 SDG Goals: Quality Education, Gender Equality, Affordable Energy, Industry Innovation Her research focuses on advanced electronics and quantum technologies, including: Logic-in-memory computing Quantum computing architectures Microwave imaging for medical and agricultural applications CAD tools for emerging nanotechnologies Embedded systems for bee health monitoring IoT solutions for bio-waste valorization Publications show strong expertise in quantum computing, nanocomputing, and microwave imaging, with recent trends emphasizing quantum optimization frameworks, in-memory architectures, and IoT-based agricultural technologies. She supervises PhD students in areas like quantum machine learning algorithms, predictive on-board systems, and quantum hardware design. Collaborations span multiple disciplines, including medical device development and agricultural electronics. Patents include innovations in microwave imaging, racetrack memory logic functions, and in-memory computing devices.
Stefan Hougardy is a Professor at the Research Institute for Discrete Mathematics, part of the Mathematisch-Naturwissenschaftliche Fakultät at the University of Bonn. He is actively engaged in research and teaching, with a focus on discrete mathematics and combinatorial optimization. He contributes to academic governance through roles in examination boards, teaching mentoring, and faculty committees. Stefan Hougardy's research lies at the intersection of theoretical computer science and practical optimization. His primary interests include approximation algorithms, the Traveling Salesman Problem (TSP), Steiner trees, graph theory, and VLSI design automation. He develops efficient algorithms for NP-hard problems and analyzes their theoretical performance guarantees. His work often bridges theory and application, particularly in electronic design automation and mathematical programming. His recent publications demonstrate a strong focus on the complexity and approximation of combinatorial optimization problems. Key themes include the analysis of local search heuristics like k-opt for TSP, edge elimination techniques, fast matching algorithms, and optimal legalization in chip design. His work combines rigorous theoretical analysis with practical implementation and computational experiments. MPC 'Outstanding Paper of the Year' Award 2024 Stefan Hougardy supervises graduate students and leads seminars on discrete mathematics and optimization. He is involved in the Bonn International Graduate School of Mathematics and the Hausdorff Center for Mathematics, contributing to doctoral education and mentoring. While specific grant details are not listed, his sustained research output and leadership roles suggest active funding support. He also contributes to curriculum development and academic quality assurance through various institutional committees. He is affiliated with the Research Institute for Discrete Mathematics at the University of Bonn, a leading center for combinatorial optimization and algorithmic research. The institute is closely linked with the Hausdorff Center for Mathematics, fostering collaboration in discrete and applied mathematics.
Andrea Costamagna is a researcher affiliated with the École Polytechnique Fédérale de Lausanne (EPFL), working within the School of Computer and Communication Sciences and the Department of Communication Systems. His research focuses on logic synthesis, digital circuit design, and the intersection of machine learning with hardware implementation. His work includes optimizing digital circuits using techniques like resynthesis, resubstitution, and decomposition, with applications in FPGA design and low-power systems. Recent publications explore symmetry-based synthesis, glitch-aware power minimization, and the use of resistive switching devices in machine learning hardware. His research also extends to quantum physics modeling with deep learning.
Alan H. Barr is a Professor of Computer Science at the California Institute of Technology (Caltech), affiliated with the Division of Engineering and Applied Science and the Computation & Neural Systems (CNS) department. He is a founding member of the Caltech Computer Graphics Group and a leader in developing mathematically rigorous methods for computer graphics and predictive modeling. His research focuses on enhancing computational modeling accuracy through approaches like interval analysis and constraint-based systems. Notable contributions include deformable models, quaternion interpolation, and cellular simulation frameworks. He has advised over 20 graduate students, many of whom became industry leaders at Pixar, Microsoft Research, and academic institutions like NYU and Brown University. Awards include the ACM SIGGRAPH Achievement Award (1988) and ACM Fellow (1995). Research Interests: Predictive modeling with error bounds Scientific visualization and MRI data analysis Biophysical systems simulation (e.g., cellular organelles) Self-assembling robotic structures for space colonization Mathematically robust computer graphics techniques Key Collaborations: Caltech Biological Imaging Center (Beckman Institute) JPL (Jet Propulsion Laboratory) New computational substrates research (quantum/DNA computing) Recent Work: Expanding into computational biology, medical imaging optimization, and high-confidence systems for managing complex computational interactions. Active in interdisciplinary projects across Caltech divisions.
Thuy T. Le is a Professor of Electrical Engineering at San Jose State University's College of Engineering. With a distinguished career spanning several decades, he teaches graduate and undergraduate courses in digital system design, computer architecture, microprocessor systems, and related fields. His academic journey began with earning B.S., M.S., and Ph.D. degrees from the University of California, Berkeley. Professor Le's research interests encompass a broad spectrum of cutting-edge technological domains. His primary focus areas include System-on-Chip (SoC) and Embedded System Design, Hardware Accelerators for complex algorithms, Quantum Computing, implementation of Probability theory and Monte Carlo simulation, and radiation effects on electronic devices and systems. His work bridges traditional electrical engineering with emerging computational paradigms, demonstrating a consistent ability to adapt to evolving technological landscapes while maintaining strong foundations in core engineering principles. Analysis of Professor Le's publication record reveals a consistent trajectory from nuclear reactor physics and computational methods toward modern hardware acceleration and quantum computing. His early work focused on nuclear reactor simulation and radiation shielding, then evolved to parallel computing and distributed systems, and has recently centered on hardware acceleration for complex algorithms, quantum computing applications, and AI hardware. This progression demonstrates his ability to transition between major technological paradigms while maintaining expertise in computational methods and hardware implementation. Professor Le has demonstrated significant leadership in professional service, having served as keynote speaker, general chair, technical program chair, session chair, reviewer, and committee member for numerous international conferences. His service extends beyond academia through his role as Co-Founder and Advisor of the Vietnamese Strategic Ventures Network and Chairman of the Board of the United States–Vietnam Foundation. In his educational role, Professor Le has made substantial contributions to engineering curriculum development and assessment. He has taught a wide range of courses including EE271 (Advanced Digital System Design), EE210, EE250, and various project/thesis courses. His research advising spans digital system design, ASIC, SOC, and hardware accelerators. He has also collaborated with local companies on projects related to high-performance system architectures, parallel algorithms, digital arithmetic, and System-on-Chip verification.
Carl-Mikael Zetterling is a Professor and Head of Department at Kungliga Tekniska Högskolan (KTH) in Stockholm, Sweden, affiliated with the School of Electrical Engineering and Computer Science (ICT) and the Electronics and Embedded Systems department. His research focuses on process technology and device design for high-temperature, high-power silicon carbide (SiC) electronics, expanding into SiC-based analog and integrated circuits. He has authored over 300 publications, including books on SiC process technology and plagiarism prevention. Dr. Zetterling has held leadership roles such as Vice Dean of the School of ICT (2013–2017) and teacher representative on KTH's faculty board. He has collaborated internationally at Stanford University, Kyoto University, and Kyoto Institute of Technology. His work addresses applications in extreme environments, including Venus exploration and fusion reactor monitoring, with a focus on radiation tolerance and thermal resilience. The 15 most recent publications highlight trends in wide bandgap semiconductors, gamma irradiation effects on SiC devices, and high-temperature integrated circuits. His articles span structural health monitoring with machine learning, novel SiC diode designs, and radiation-hardened electronics. Key contributions include advancements in self-aligned contacts, trench MOSFETs, and compact modeling for extreme conditions. While no formal awards are listed, his roles in technical program committees (TMS Electronic Materials Conference, IEEE SISC Conference) and editorial work demonstrate significant academic service. He teaches courses ranging from digital design to high-temperature electronics, overseeing degree projects in embedded systems, communication, and nanotechnology.
Dr. Patrick W. C. Ho is a Lecturer in the Department of Electrical & Computer Systems Engineering (ECSE) at Monash University Malaysia School of Engineering. He holds a PhD in Electronics Engineering from the University of Nottingham Malaysia Campus (2016), with research focusing on non-volatile FPGA architectures using memristors. His academic journey includes roles as a Scholarly Teaching Fellow and unit coordinator for courses like ECE2131 Electrical Circuits and ECE4063 Large Scale Digital Design. He has industry experience with Intel Microelectronics and Altera Corporation, alongside teaching A-level Physics at Methodist College Kuala Lumpur. Education: BEng (First Class Honours) in Engineering (2009) MSc in Science (2012) PhD in Electronics Engineering (2016) Research Interests: Dr. Ho specializes in memristor-based non-volatile memory systems, VLSI design, and FPGA architectures. His work bridges hardware design with emerging materials, as seen in his Q1 journal article on memristive LUTs. Collaborations with CAD-IT expand his focus into AI, image processing, and object recognition. Recent projects include studies on memristor substrate performance (2023–2026) and UAV communication reliability (2021–2024). Teaching and Industry Engagement: As ECSE’s Industrial Training Advisor and IAP representative, he actively connects academic curricula with industry needs. His teaching spans foundational engineering courses and advanced digital design modules. Labs and Collaborations: Active in CAD-IT partnerships for student FYP co-sponsorship. Research groups focus on nanotechnology, machine learning integration in UAV systems, and memristor material analysis.
Luca Sterpone is a Full Professor at the Department of Control and Computer Science (DAUIN), Politecnico di Torino. He serves as Head of the Control and Computer Engineering Department (2023-2027), coordinates the Aerospace and Safety Computing Lab, and is a member of the Academic Senate and Power Electronics Innovation Center (PEIC). His research spans reconfigurable computing, fault tolerance, and radiation effects analysis in electronic systems. Professor since 2021 Department Head (DAUIN) since 2023 Coordinates international collaborations with ESA, AMD Xilinx, NVIDIA, and Thales Alenia Space Develops radiation-hardened FPGA tools (SETA, VERI-Place, PyXEL) 2007 EDAA Outstanding Dissertation Award and 2005 IEEE Best Paper Award Research Focus : Designing radiation-tolerant systems for aerospace, including fault-tolerant AI accelerators, FPGA reliability, and software-based error mitigation. He investigates soft error propagation in nanoscale circuits and develops tools for radiation sensitivity analysis in VLSI. His work integrates hardware-software co-design for mission-critical applications. Awards : EDAA Outstanding Dissertation Award (2007) IEEE European Test Symposium Best Paper (2005) SMACD Best EDA Tool Award (2018) ARC Best Paper candidate (2018) Teaching : He leads courses in Reconfigurable Computing (PhD level), GPU Programming , and Operating Systems . He has formal responsibility for teaching roles across 9 bachelor's and 7 master's years, and mentors multiple PhD students. Collaborations : Coordinates with the European Space Agency (ESA), University of Bielefeld, Universidad de Sevilla, and industrial partners like AMD Xilinx, NVIDIA, and General Motors. He leads projects such as RESCHIP4EU, VEGAS, and TERRAC for radiation-hardened computing solutions.
Guido Masera is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he has been actively involved in teaching and research for over two decades. He serves as a Member of the Board of Directors, Member of the GEDI Observatory for Gender Equality, Diversity and Inclusion, and Member of the Permanent University Observatory for monitoring the academic supply chain. His research interests span across channel decoders, circuits for communications, cryptography, deep learning, digital integrated circuits, field programmable gate arrays (FPGA), and hardware design. His work focuses on VLSI architectures for image and video coding, digital architectures for error correcting codes, application specific approximate computing, VLSI architectures for machine learning, digital architectures for bio-inspired processing, digital architectures for post-quantum cryptography, bio-inspired electronics for robotics and biomedical applications, RISC-V extensions and hardware accelerators, and circuit architectures for efficient machine learning and artificial intelligence. His recent publications (2025) demonstrate a strong focus on RISC-V architecture, particularly in the context of cryptographic implementations, hardware security, and post-quantum cryptography. His research group VLSILAB is actively engaged in cutting-edge research in hardware security, efficient processor design, and specialized computing architectures. Among his notable recognitions are the Premio Francesco Carassa awarded by the Telecommunications and Information Technologies Group Association (gtti) in 2010, and his recognition as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) since 2007. He also serves as an Associate Editor for several prestigious journals including ELECTRONICS (2019-present), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (2015-2019), and IET CIRCUITS, DEVICES & SYSTEMS (2013-2016). Professor Masera has advised numerous PhD students working on advanced topics in VLSI design, post-quantum cryptography, hardware accelerators, and machine learning implementations. His current research projects include ISOLDE (2023-2026) and TRISTAN (2022-2025), both EU-funded projects focused on RISC-V technology and domain-specific ecosystems. He leads the VLSILAB research group at the Department of Electronics and Telecommunications, which focuses on cutting-edge research in VLSI architectures, hardware security, and specialized computing systems. The group collaborates with industry partners and participates in major European research initiatives.
Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.
Irith Pomeranz is the Cadence Professor of Electrical and Computer Engineering at Purdue University's College of Engineering. Her research focuses on advanced testing methodologies for VLSI circuits, including functional test compaction, fault diagnosis, and built-in self-test (BIST) techniques. She is affiliated with the Department of Electrical and Computer Engineering and has contributed extensively to improving test efficiency and fault coverage in digital circuits. Her work addresses challenges such as aging effects, transition faults, and path delay faults, with a particular emphasis on practical implementations for industrial applications. Key areas of interest include modular test sequences, configuration-based compaction, and dynamic testing strategies for in-field environments. She has developed algorithms for dual-target diagnostic testing and synchronization mechanisms for online fault detection in logic blocks. Research Trends in her publications emphasize innovations like storage-based BIST schemes, adaptive test scheduling, and shared test data architectures. These advancements aim to reduce test data volume, improve fault coverage, and enhance reliability in modern integrated circuits. Her work often bridges theoretical foundations and practical hardware implementations. Grants & Advising : While specific grants or student advisees are not listed, her prolific publication record indicates active involvement in research projects and graduate supervision within Purdue's ECE department. Labs & Teams : Her contributions are likely tied to Purdue's VLSI and testing research groups, though specific lab affiliations are not detailed in the provided text.
Prof. Dr.-Ing. H. Siegfried Stiehl is a retired Senior Professor (until Sept 2021) at the Department of Informatics, University of Hamburg. He previously held roles including Dean of the Faculty of Mathematics, Computer Science, and Natural Sciences (2001–2006), Vice President for Research (2007–2013), and Head of the Image Processing Research Group. His academic journey includes a PhD from TU Berlin (1980) and a Habilitation in Computer Vision (1987). Education: 1973: Ing. Degree in Ingenieur-Informatik, Fachhochschule Furtwangen 1976: Diploma in Computer Science, TU Berlin 1980: Dr.-Ing. Dissertation on medical image processing, TU Berlin Research focuses on Computer Vision , Computational Neuroscience , and Cognitive Science , with contributions to medical image registration, 3D landmark detection, and biomechanical modeling. Key projects include the EU-funded 'COVIRA' consortium (1989–1995) and leadership in the SFB 950 'Manuscript Cultures' project (2015–2019). His 110+ publications span biomedical image registration, elastic deformation algorithms, and real-time signal processing. Notable collaborations include work with institutions like the University of Pennsylvania, University of Birmingham, and Philips Research. Leadership roles include organizing scientific events, serving on editorial boards (e.g., Biological Cybernetics), and founding the Interdisciplinary Nanoscience Center Hamburg (INCH) in 2001. His research has addressed challenges in neurosurgical interventions, VLSI implementation of neural networks, and interdisciplinary education.
Professor Ahmed Hemani is a faculty member at the Division of Electronics and Embedded Systems, KTH Royal Institute of Technology, affiliated with the Digital Futures Faculty. He holds the role of PI for the project 'New Chip Architectures for Industrial Vision' and leads research in reconfigurable computing, memristor-based systems, and hardware acceleration for AI and edge computing. His work bridges theoretical computer science with practical VLSI design and embedded systems development. He actively contributes to cross-disciplinary initiatives at Digital Futures, a joint center with Stockholm University and RISE Research Institutes of Sweden focused on digital innovation. His research emphasizes scalable FPGA/HPC architectures, low-power neuromorphic systems, and optimization techniques for custom silicon solutions. Current projects include a Lego-inspired edge AI framework and memristor-driven MIMO acceleration. Teaching responsibilities span advanced courses in SOC design, digital system verification, and embedded systems. He supervises advanced-level degree projects across computer engineering and ICT innovation specializations, emphasizing hands-on hardware-software co-design methodologies. Recent publications highlight innovations in memristor applications, FPGA-based acceleration, and reconfigurable architectures for neural networks and bioinformatics. His work addresses challenges in dark silicon utilization, energy-efficient computation, and high-performance embedded systems.
