جست‌وجوی استاد و پژوهشگر

Mian M. Hamayunمشاهده پروفایل

دانشیار

• Computer Science
• Transaction Level Modeling (TLM)
• MPSoC Simulation
• +۱۵ مورد دیگر

Mian M. Hamayun is an Associate Professor of Computer Science and Head of Subject Group at the University of Birmingham Dubai campus, part of the College of Engineering and Physical Sciences. He holds a PhD in System Modelling, Simulation & Virtualization from the University of Grenoble Alpes, France, and has academic qualifications from Joseph Fourier University and COMSATS Institute of Information Technology, Pakistan. PhD in System Modelling, Simulation & Virtualization, University of Grenoble Alpes, 2013 MS in Informatics (Parallel & Distributed Systems), Joseph Fourier University, 2009 MSE in Software Engineering (Gold Medalist), COMSATS, 2005 PGCHE, University of Birmingham, 2021 FHEA and SFHEA, University of Birmingham (2021, 2024) His research spans Transaction Level Modeling (TLM) , MPSoC simulation , cloud computing , virtualization , Internet of Things/Vehicles , edge AI , and TinyML . He focuses on performance estimation, binary translation, and system-level simulation for embedded and distributed systems. The recent publications reflect a strong trend in IoT and vehicular networks , secure telemedicine , cloud orchestration , and embedded system simulation . His work integrates virtualization with security, real-time constraints, and machine learning on edge devices. Senior Fellow of the Higher Education Academy (SFHEA), 2024 Fellow of the Higher Education Academy (FHEA), 2021 Dr. Hamayun has supervised multiple research students and contributed to projects involving fatigue detection, person re-identification, retinal image analysis, and secure surgery frameworks. He has taught core computer science courses including Operating Systems, Networks, Data Structures, Algorithms, and Functional Programming at both undergraduate and postgraduate levels. His prior roles include Assistant Professor at NUST SEECS, R&D Engineer in France, and Lecturer at IUT1. He leads research in virtual prototyping and edge intelligence at the Dubai campus, contributing to smart city and cognitive systems initiatives. His lab work involves hybrid simulation environments, secure automotive platforms, and distributed IoT systems.

• Embedded Systems
• Computer Architectures
• Operating Systems
• +۷ مورد دیگر

Ole Blaurock is a Professor of Computer Science at the University of Applied Sciences Lübeck, where he is affiliated with the Department of Electrical Engineering and Computer Science. His expertise lies in embedded systems, computer architectures, operating systems, and systems programming. Research Interests: His research focuses on embedded systems design, particularly in the areas of hardware/software codesign, SystemC-based modeling, platform-based SoC development, and reuse of C-models. He has contributed significantly to methodologies promoting legacy model reuse and modular design frameworks. His work bridges theoretical design approaches with industrial applications in semiconductor systems. Recent Publications Trends: His recent publications, spanning from 2001 to 2011, show a consistent focus on SystemC-based design flows, TLM simulation, and modular verification frameworks. A notable contribution includes editing proceedings on robotic sailing, indicating interdisciplinary interests in autonomous marine systems. Scientific Awards: No awards mentioned in the provided text. Advising and Grants: Information about students, advising, or grants is not available in the provided text. Labs and Teams: Ole Blaurock is associated with the Competence Center CoSA (Cooperative Systems and Automation) at the University of Applied Sciences Lübeck, indicating active engagement in applied research and technology transfer in embedded and cooperative systems.

David Greavesمشاهده پروفایل

مدرس ارشد

• Computer Architecture
• Programming Languages
• Semantics and Verification
• +۳ مورد دیگر

David Greaves serves as a University Senior Lecturer in the Department of Computer Science and Technology at the University of Cambridge, where he conducts research and teaches undergraduate courses including Databases (Part IA) and Programming in C and C++ (Part IB). His academic work focuses on bridging hardware and software systems through innovative compilation techniques and architectural design. His research spans computer architecture, programming languages, semantics and verification, and systems and networking, with particular emphasis on hardware-software co-design, memory safety mechanisms, and FPGA-based acceleration. Greaves has developed specialized compiler frameworks like Kiwi for translating high-level programs into hardware implementations, and created security models such as FRAMER for capability-based memory protection. Analysis of his recent publications reveals a consistent focus on compiler infrastructure for hardware acceleration, with significant contributions to Bluespec Verilog compilation, dataflow intermediate representations, and cache-friendly security models. His work demonstrates strong interdisciplinary connections between formal methods, hardware design, and systems security, often targeting practical implementations in FPGA environments. Greaves maintains active involvement in hardware description language development and power analysis tools, as evidenced by his contributions to TLM Power and other electronic design automation frameworks. His research approach consistently emphasizes practical toolchain development alongside theoretical foundations.

• Embedded Systems
• Cyber-Physical Systems
• Computer Architecture
• +۷ مورد دیگر

Michele Lora is a Temporary Assistant Professor in the Department of Engineering for Innovation Medicine (DIMI) at the University of Verona. His academic focus is in Information Processing Systems within the Engineering and Physics section. Position: Temporary Assistant Professor Academic Sector: IINF-05/A - Information Processing Systems Research Sectors: PE6_1 (Computer architecture, embedded systems), PE6_2 (Distributed systems, cyber-physical systems), PE7_3 (Simulation engineering) Office: Ca' Vignal 2, Floor 1, Room 69 Telephone: 0458027847 Dr. Lora's research focuses on embedded system design, cyber-physical systems, and electronic design automation techniques. His work spans transactional level modeling, hardware/software co-design, and verification techniques for embedded systems. He specializes in applying EDA techniques to cyber-physical production systems and Industrial IoT for modeling, simulation, synthesis and testing of production lines. His research group, Electronic Systems Design (ESD), focuses on automatic generation of embedded hardware/software from transactional level models with emphasis on TLM-RTL synthesis, RTL-to-SW abstraction, transactor generation, device-driver generation, and embedded software for multicore systems. Dr. Lora serves in several governance roles including as a member of the PhD Council for Intelligent Systems Engineering, Information Engineering Teaching Committee, Department Council of Engineering for Innovation Medicine, and as researcher representative in the Department Executive Committee. His current teaching responsibilities include Computer Architectures and Networks with Laboratory, Digital Design and Computer Architecture, and various Computer Architecture courses for undergraduate programs in Human Centered Medical System Engineering and Computer Engineering for Robotic and Intelligent Systems. Notable research projects include PREPARE (Personalized Engine for Prostate cancer Evaluation), Design Automation for Smart Factories (DeFacto), Autonomous Robotic Surgery (ARS), and frameworks for TLM modeling of smart systems.

• Network-on-Chip (NoC)
• Embedded Systems
• Fault Tolerant Design
• +۴ مورد دیگر

Martin Radetzki is a full Professor at the Institute for Computer Architecture and Parallel Systems (University of Stuttgart) , specializing in Embedded Systems . His work focuses on network-on-chip (NoC) design, fault tolerance, memory optimization, and simulation frameworks. Key research areas: NoC synthesis, deadlock-free routing, performability analysis, and power-efficient memory subsystems Recent publications emphasize integer linear programming frameworks for co-designing floorplanning and routing, chiplet-based systems , and machine learning-enabled performance evaluation His methodologies address cross-layer challenges in NoC design, combining formal optimization with practical implementation for heterogeneous processing elements. Collaborative projects include fault resilience analysis, parallel simulation techniques, and memory allocation strategies for SoCs. Dr. Radetzki supervises research with students like Shuang Liu and Manuel Strobel , contributing to IEEE Transactions on Computers , ACM TECS , and conferences such as DATE and MCSoC . Current work explores optimal routing topologies for emerging chip architectures.