Dr. Chengmo Yang is a Professor in the Department of Electrical and Computer Engineering at the University of Delaware, with a joint appointment. She received her PhD and MSc in Computer Science from the University of California, San Diego, and a BSc in Microelectronics from Peking University, China. PhD, University of California, San Diego MSc, University of California, San Diego BSc, Peking University, China Her research focuses on enhancing security, reliability, non-volatility, and energy efficiency in embedded systems, cyber-physical systems (CPS), and Internet-of-Things (IoT). She leads the Computer Architecture, Reliability, and Security (CARES) group and has authored over 70 peer-reviewed publications. Recent publications emphasize neural network accelerators, non-volatile memory (NVM) optimization, and security frameworks for embedded systems. Her work explores fault tolerance, wear leveling, and side-channel attack mitigation in NVM-based FPGAs, STT-RAM, and SSDs. National Science Foundation Career Award (2013) University of Delaware Mid-Career Faculty Excellence in Scholarship Award (2020) Best paper award at ICESS (2019) Three best paper nominations at DAC, DATE, and GLSVLSI (2019) Dr. Yang serves as Associate Editor for IEEE TCAD and ACM TODAES. She is the Diversity & Inclusion Representative for IEEE CEDA and has organized numerous conferences including Technical Program Chair for CODES-ISSS 2022. Her lab has hosted current and former students like Fanruo Meng (PhD candidate), Fateme Hosseini (Qualcomm), and Patrick Cronin (Intel), focusing on graduate-level research in hardware security and reliability.
Shweta Shinde is an Assistant Professor in the Department of Computer Science at ETH Zurich where she leads the Secure & Trustworthy Systems (SECTRS) research group. She is also a member of the Institute of Information Security and the ZISC Center at ETH Zurich. Her work bridges theoretical foundations with practical implementations in hardware and system security. Dr. Shinde's research focuses on the intersection of trusted computing, system security, and program analysis. Her group investigates both foundational aspects of security to protect phones, servers, and accelerators, as well as practical aspects of realizing these solutions through large-scale system building. Her work spans hardware security primitives, trusted execution environments, confidential computing, and secure system design across multiple platforms including mobile devices, cloud infrastructure, and blockchain systems. Her publication record demonstrates significant impact in the field, with numerous papers in top security venues including IEEE S&P, USENIX Security, CCS, and NDSS. Her research has uncovered critical vulnerabilities in major hardware security technologies like Intel SGX and AMD SEV-SNP while also proposing novel frameworks for building more secure systems. The work spans multiple domains including hardware security, cloud security, mobile security, and blockchain security, with a consistent thread of identifying and addressing fundamental security challenges in trusted computing. Among her notable achievements are multiple best paper awards including at SysTEX 2025 and nominations at DATE 2025, a Distinguished Paper Award at IEEE S&P 2024, and recognition as a Most Innovative Research Pwnie Award Nominee in 2024. Her work on WeSee received particular attention for breaking AMD SEV-SNP through novel interrupt-based attacks. Dr. Shinde actively mentors PhD students including Mark Kuhne, Supraja Sridhara, Mélisande Zonta-Roudes, Benedict Schlüter, Andrin Bertschi, and others. She teaches courses on Systems Security, Information Security Lab, Seminar on Systems Security, and Current Topics in Information Security at ETH Zurich. Her service to the community includes extensive program committee work for major security conferences including Oakland (S&P), NDSS, USENIX Security, and CCS, where she has served as track co-chair and program co-chair for several workshops.
Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.
Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.
Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.
Srijan Kumar is an Assistant Professor in the School of Computational Science and Engineering at Georgia Institute of Technology's College of Computing. His research focuses on data science, AI for security, and online safety, addressing challenges in detecting malicious users, misinformation, and enhancing AI robustness. His work has been deployed in platforms like Flipkart and Wikipedia, and recognized through awards such as the NSF CAREER and Forbes 30 Under 30. Education: B.Tech from Indian Institute of Technology, Kharagpur Ph.D. in Computer Science from University of Maryland, College Park Postdoctoral training at Stanford University Research Interests: Multi-modal/multi-lingual detection of harmful content and users Adversarial robustness of AI models Graph and network analysis for early detection Responsible recommender systems Awards & Grants: NSF CAREER Award (2023) Kavli Fellow (2022) Facebook/Adobe Faculty Awards NSF Convergence Accelerator Phase II grant ($5M) Advising & Labs: Leads the CLAWS Lab, advising over 20 students. Active in mentoring through conferences and NSF-funded projects.
Prof. Dr. Timothy Roscoe is a Full Professor in the Department of Computer Science at ETH Zurich. His research focuses on operating systems, networking, and distributed systems. He was inducted as an ACM Fellow in 2014 for contributions to these fields. Previously, he worked at Intel Research Berkeley, UC Berkeley (Adjunct Professor), and Sprint Labs. His work includes foundational contributions to systems like PlanetLab, P2 Declarative Networking, and the Nemesis OS. Roscoe holds a PhD from the University of Cambridge and has led projects in cloud computing, wide-area network measurement, and secure systems design. His current research emphasizes hardware-software co-design, formal verification of systems, and scalable memory architectures. Education: PhD in Computer Science, University of Cambridge (1995) Key Roles: Principal Researcher at Intel Berkeley Lab, Visiting Researcher at National ICT Australia Research Highlights: Contributions to distributed systems (PlanetLab), declarative networking (P2), and secure microkernels (seL4 integration). Current projects address challenges in disaggregated memory systems, coherent interconnects, and trustworthy embedded systems. Awards: ACM Fellow (2014), numerous grants and industry collaborations. Labs/Teams: Systems Group at ETH Zurich, focusing on OS design, hardware architectures, and formal methods.
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
Marco Platzner is a Professor for Computer Engineering at Paderborn University , Germany. He serves as the Dean of Research for the Faculty of Computer Science, Electrical Engineering and Mathematics and heads the Department of Computer Science. Previously, he held research positions at ETH Zurich, Stanford University, GMD (now Fraunhofer IAIS), and Graz University of Technology. Education: Diploma and PhD in Telematics (Graz University of Technology, 1991 and 1996), Habilitation in Hardware-Software Co-Design (ETH Zurich, 2002) Research Interests focus on reconfigurable computing, approximate computing, self-* computing, and embedded systems. His work addresses hardware security, FPGA design, and sustainable AI in data centers. Current projects include energy-efficient AI through deep neural network approximation for FPGAs (EKI-App) and lifecycle sustainability of socio-technical systems (SAIL). Publication Trends show expertise in FPGA security, approximate circuit synthesis, robotics, and hardware acceleration. Collaborations span robotics (ROS 2 integration), AI (transformer optimization), and cybersecurity (Trojan detection). Scientific Awards: ACM SIGDA Hall of Fame (2020) Significant Paper Award (FPL 2015) Best Paper Awards at IEEE ISVLSI (2024), ARC (2018), IEEE ReConFig (2015), and others Weierstraß Prize for Teaching (2008) Leadership Roles include membership in the board of Paderborn Center for Parallel Computing (PC2) and the Jenny Aloni Centre for Early Career Researchers. He has contributed to EU FP7 FET project EPiCS and German priority programs on embedded systems and organic computing.
Jean-Claude Besse is a Lecturer in the Department of Physics at ETH Zürich, specializing in superconducting circuits and quantum optics. His research focuses on quantum computing, microwave photonics, and artificial atoms. Research Interests: Besse works on the fabrication of superconducting circuits, modular quantum computing processors, and microwave quantum optics using artificial atoms. His work includes single-photon detection, parity measurements, entanglement stabilization, and quantum networking. He has developed technologies like high-fidelity multiplexed readout and tunable ZZ gates. Key Contributions: Besse led breakthroughs in non-destructive single-photon detection, deterministic remote entanglement, and loophole-free Bell inequality violations. His research enables error-corrected quantum communication protocols and scalable microwave quantum systems. Publications Trends: Recent articles emphasize modular quantum architectures, entanglement stabilization, and microwave photon engineering. Topics include cluster state generation, defect mode mitigation, and reinforcement learning for quantum feedback systems. Labs & Teams: Affiliated with the Laboratorium für Festkörperphysik at ETH Zürich, Besse contributes to advancing superconducting quantum technologies and microwave quantum optics.
Dr. Kyle Jamieson is a Professor of Computer Science at Princeton University, leading the Princeton Advanced Wireless Systems (PAWS) lab within the Department of Computer Science. He is also Affiliated Faculty in the Department of Electrical and Computer Engineering. His research focuses on wireless networking systems, 5G architecture, IoT networks, and quantum computing applications in wireless communication. He has pioneered work in reconfigurable intelligent surfaces, MIMO detection algorithms, and metamaterials for millimeter-wave networks. Dr. Jamieson has developed courses such as COS 597S: Recent Advances in Wireless Networks (graduate seminar), COS 463: Wireless Networks , and COS 418: Distributed Systems . His teaching emphasizes interdisciplinary approaches to networking challenges, including physical-layer design, computational structures for wireless processing, and cross-layer optimization. His lab’s research spans smart surfaces for 5G networks, quantum annealing for MIMO processing, and edge computing for live video analytics. Recent work includes deploying reconfigurable metamaterials for enhanced mmWave networks and developing tools like NR-Scope for 5G telemetry. While no awards are listed in the provided text, his contributions to wireless systems have advanced both academic and industrial applications in areas such as network resilience, IoT scalability, and quantum-enabled wireless processing. Dr. Jamieson’s advising focuses on graduate and undergraduate students working in wireless systems, though specific advisee names are not provided. His lab collaborates on projects like Wall-Street for roadside networking and Spider for multi-hop mmWave video analytics. External collaborations include work with Microsoft Research and guest lecturing roles at Berkeley. His research bridges theoretical foundations with practical implementations, often addressing real-world challenges in wireless infrastructure and next-generation communication systems.
Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.
Vijay Laxmi is a Professor in the Department of Computer Science and Engineering at Malaviya National Institute of Technology (MNIT) Jaipur, India. With over a decade of active research publication from 2014-2024, Dr. Laxmi has established themselves as a prominent researcher in network security, Android security systems, and Network-on-Chip architectures. Their work demonstrates consistent collaboration with Manoj Singh Gaur and numerous doctoral students at MNIT Jaipur. Dr. Laxmi's research interests span Network Security, Android Security, Malware Analysis, Network-on-Chip Architectures, Routing Protocols, Side-Channel Attacks, Wireless Networks, and Mobile Security. Their work bridges theoretical security frameworks with practical implementations, particularly in mobile and embedded systems. Recent publications indicate a growing focus on AI-based security approaches including GAN applications for fuzzing and deep learning for image dehazing. The research trajectory shows increasing sophistication in security analysis techniques, evolving from basic malware detection to advanced side-channel attack analysis and sophisticated network security protocols. Recent publications demonstrate expertise in both theoretical frameworks and practical implementations with applications in real-world security challenges. Dr. Laxmi has mentored numerous graduate students including Vineeta Jain, Anugrah Jain, Sonal Yadav, Mohit Singh, and Gaurav Singal, who appear as co-authors across multiple publications. Their collaborative network extends to researchers at international institutions, indicating strong academic connections beyond their home institution.
Wolfgang Kunz is a Full Professor (C4, W3) and Chair of Electronic Design Automation at the Technische Universität Kaiserslautern since 2001. His academic career spans multiple prestigious institutions, including Goethe-University Frankfurt/Main and the University of Massachusetts, Amherst. He has held leadership roles such as Dean (2005-2007) and Vice-Dean (2007-2009) at TU Kaiserslautern. Habilitation (Dr. rer. nat. habil.), Computer Science, University of Potsdam (1996) Doctoral degree (Dr.-Ing.), Electrical Engineering, University of Hannover (1992) Dipl.-Ing. degree, Karlsruhe Institute of Technology (1989) His research focuses on hardware verification, security, and optimization, particularly in embedded systems and processors. His work on formal verification methods has been commercialized by companies like Synopsys, Mentor Graphics, and Siemens EDA. His 2016-2021 publications address critical security issues such as Spectre/Meltdown and introduce innovative verification frameworks adopted by industry leaders like Infineon and OneSpin Solutions. Scientific awards include the IEEE Fellow (2006), German IT Society Award (2005), and TU Kaiserslautern Distinguished Teaching Award (2016). He has served on editorial boards of major journals and coordinated the Erasmus Mundus European Master Program in Embedded Computing Systems since 2010. Key students: Jörg Bormann, Raik Brinkmann, Tobias Ludwig Collaborations: Siemens EDA, Infineon, AbsInt, Intel SCAP Spin-offs: LUBIS EDA, OneSpin Solutions
Anil Madhavapeddy serves as Professor of Planetary Computing at the University of Cambridge's Department of Computer Science and Technology and directs the Cambridge Centre for Carbon Credits (4C). A Fellow of Pembroke College, he integrates systems research with environmental conservation through the Computer Laboratory's Environment and Energy Group. His career spans industry leadership (NetApp, Citrix, Intel), academic appointments (Cambridge, Imperial, UCLA), and entrepreneurial ventures (XenSource, Unikernel Systems, Docker). Madhavapeddy earned his PhD at Cambridge's Computer Laboratory in 2006. His research bridges computational systems and planetary-scale environmental challenges, with deep expertise in open-source development (OCaml, Xen, Docker, OpenBSD) and technology strategy advising for organizations including Zededa, Tezos Foundation, and Tarides. His work centers on environmental computing and climate informatics, leveraging distributed systems and functional programming to develop sensing infrastructure for conservation. Recent projects focus on carbon credit systems, AI-driven biodiversity monitoring, and sustainable computing architectures that minimize ecological footprints while maximizing analytical capability. Analysis of his 2025 publications reveals a concentrated effort on AI-integrated conservation tools, privacy-preserving carbon accounting, and energy-efficient computing. Key themes include spatial networking for ecological data, LLM-enhanced evidence retrieval in conservation science, and novel metrics for extinction risk assessment—demonstrating computational innovation applied to urgent planetary boundaries. No scientific awards were documented in the source material. Madhavapeddy advises multiple technology firms on strategic development while leading the Cambridge Centre for Carbon Credits, though specific grant funding details remain unreported. He actively contributes to the Environment and Energy Group at Cambridge's Computer Laboratory and directs the interdisciplinary Cambridge Centre for Carbon Credits (4C). His open-source leadership spans critical infrastructure projects including OCaml, Xen, and Docker, fostering collaborative development communities that underpin modern cloud and container technologies.
