جستجوی استاد راهنمای دانشگاهی

• Computer Architecture
• CPU Microarchitecture
• Accelerator Design
• +۳ مورد دیگر

Dr. Dong Kai Wang is a Teaching Assistant Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research focuses on leveraging machine learning for computer architecture advancements, particularly in CPU and accelerator microarchitecture design. He is interested in improving system performance and energy efficiency through innovative hardware solutions. Wang's recent work, supported by a grant from Samsung, explores using accelerators to offload tasks traditionally handled by CPUs, aiming to enhance efficiency without major architectural overhauls. His approach involves a lightweight controller to translate CPU machine code for use on reconfigurable accelerators, minimizing chip area costs while maximizing performance gains. This research builds on his doctoral work under Nam Sung Kim, now a co-PI on the project. He has contributed to the field through editorships in journals such as Integration, the VLSI Journal and IEEE Transactions on Computers. His efforts have been recognized with the AMD HACC Outstanding Researcher Award (2024). Wang teaches courses in digital systems, computer organization, and VLSI system design, reflecting his commitment to both research and education. Wang has also secured a patent (US-20240211393-A1) for "Leveraging Processing in Memory Registers as Victim Buffers," further underscoring his innovative contributions to hardware design. His research lab focuses on advancing hardware-software co-design and next-generation computing architectures.

K. Psarakisمشاهده پروفایل

پژوهشگر

• Cloud Computing
• Stream Processing
• Distributed Systems
• +۸ مورد دیگر

K. Psarakis is a researcher in the field of Data-Intensive Systems, focusing on cloud computing, stream processing, and distributed dataflows. Their work bridges theoretical and practical challenges in cloud-native applications and scalable systems. Institution: Affiliated with Data-Intensive Systems Research Focus: Cloud transaction management, autoscaling, geospatial data platforms, and fault tolerance Research Trends Recent publications like Styx and CheckMate highlight innovations in transactional stateful functions and checkpointing protocols. Psarakis also contributes to geospatial data federation (e.g., Topio ) and schema matching techniques ( Valentine ). Collaborations Collaborates with researchers such as G. C. Christodoulou, M. Fragkoulis, and A. Katsifodimos on projects involving open-source platforms and cloud-native systems.

Nathan Beckmannمشاهده پروفایل

استاد

• Computer Architecture
• Embedded Systems
• Energy-Efficient Computing
• +۴ مورد دیگر

Nathan Beckmann is a Courtesy Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University, part of the College of Engineering. His research focuses on computer architecture, embedded systems, energy-efficient computing, and memory hierarchy design. He explores topics such as dataflow architectures, near-data computing, and cache optimization to enhance performance and reduce energy consumption in modern systems. His work spans both theoretical and applied aspects, including hardware-software co-design for reconfigurable systems, low-power IoT architectures, and novel caching strategies for emerging memory technologies like flash and MRAM. Key contributions include frameworks for ultra-low-power CGRAS, energy-minimal dataflow SoCs, and sustainable caching solutions. Dr. Beckmann's recent articles emphasize innovations in spatial dataflow programming models, task parallelism control, and polymorphic cache hierarchies. His research often targets real-world applications in edge computing, embedded systems, and high-performance datacenters.

• Database Systems
• Query Compilation
• High-Performance Computing
• +۳ مورد دیگر

Ruby Tahboub is a Teaching Assistant Professor at the Siebel School of Computing and Data Science, University of Illinois Urbana-Champaign (UIUC), since 2022. She previously served as a Visiting Assistant Professor at Purdue University (2019–2022). She holds an M.S. (2016) and Ph.D. (2019) in Computer Science from Purdue University. Her research focuses on query compilation, spatial databases, and high-performance computing, with notable contributions to Apache Spark optimization and educational tools like LIMO for programming education. She teaches courses such as Introduction to Data Mining (CS 412) and Introduction to Programming for Engineers and Scientists (CS 101). Ruby has received the Raymond Boyce Graduate Teacher Award (Purdue, 2016) and the Best Demo Award at ACM SIGSPATIAL (2015) for her work on LIMO. Her research spans database systems, compiler design, and distributed computing, emphasizing practical applications in both industry and education. Her work bridges theoretical advancements in query processing with real-world scalability challenges, particularly in spatial and heterogeneous workloads. She also advocates for innovative teaching methods to enhance programming literacy through interactive tools like map-based activities.

John Liagourisمشاهده پروفایل

استادیار

• Distributed Systems
• Databases
• Secure Analytics
• +۴ مورد دیگر

Dr. John Liagouris is an Assistant Professor at Boston University's Faculty of Computing and Data Sciences, appointed since July 2022. Previously, he served as an Adjunct Assistant Professor (2020–2022) and held roles at BU’s Hariri Institute for Computing, ETH Zurich’s Systems Group, UC Berkeley’s RISELab, and the University of Hong Kong. His research focuses on distributed systems, databases, and secure analytics, with a strong emphasis on privacy-preserving technologies in cloud environments. He earned a 5-year diploma in Electrical and Computer Engineering (2008) and a PhD (2015) from the National Technical University of Athens (NTUA). His academic journey includes visiting scholar positions at UC Berkeley and the University of Hong Kong, alongside research roles at the Athena Research Center in Greece. Liagouris’s research spans cryptographic cloud analytics, streaming state management, and spatial RDF data systems. His work on frameworks like Queryshield and TVA demonstrates expertise in securing distributed data processing. Recent trends in his publications emphasize multi-party computation and latency-conscious distributed systems. His contributions to fault-tolerant systems (e.g., Lineage Stash) and incremental routing logic (DeltaPath) highlight a focus on optimizing distributed workflows. Though no formal advising records are listed, his roles suggest active involvement in training researchers in distributed computing and cybersecurity. Labs and teams associated with his work include BU’s Hariri Institute and collaborations with institutions like ETH Zurich’s Systems Group, reflecting a networked approach to academic research.

• Image and Signal Processing
• Computer Vision
• Artificial Intelligence
• +۶ مورد دیگر

Dr. Deepayan Bhowmik is a Senior Lecturer and Director of Research at Newcastle University's School of Computing. He holds a PhD in Electronic and Electrical Engineering from the University of Sheffield. His research focuses on image/signal processing, AI, neuromorphic vision systems, and their applications in media security, remote sensing, and space research. He actively contributes to UN Sustainable Development Goals related to clean water, environmental sustainability, and responsible consumption. Grants & Collaborations: PI of £2M EPSRC-funded North East Space Communications Accelerator (2025-2029) Co-I in Airbus-funded Smart Earth Observation Satellite Constellation project (2024-2028) Lead on JPEG Trust international standard for media authenticity Research Interests: Combines theoretical advancements in signal processing with practical applications in media forensics, environmental monitoring, and heterogeneous computing. Recent work addresses AI-generated media manipulation detection and satellite imagery analysis for ecological challenges like water hyacinth infestation. Publications: Over 28 peer-reviewed articles spanning watermarking techniques, FPGA optimization, and remote sensing applications. Recent trends show increasing focus on AI-driven media security and space-based earth observation systems.

Joel S. Emerمشاهده پروفایل

استاد

• Accelerator Architectures for Sparse Computation
• Accelerator Architectures for Deep Learning
• Spatial Processing Architectures
• +۵ مورد دیگر

Joel S. Emer is a Professor of the Practice in MIT's Department of Electrical Engineering and Computer Science (EECS) and a Senior Distinguished Research Scientist at NVIDIA. His research focuses on computer architecture, processor micro-architecture, and performance modeling. He has contributed to advancements in simultaneous multithreading, cache optimization, and reliability analysis. Emer holds over 25 patents and has published over 60 papers, earning awards like the IEEE Rau Award and induction into the National Academy of Engineering. Education: Ph.D., Electrical Engineering, University of Illinois Urbana-Champaign, 1979 M.S., Electrical Engineering, Purdue University, 1975 B.S., Electrical Engineering, Purdue University, 1974 (highest honors) Research interests include accelerator architectures for sparse computation and deep learning, spatial processing, memory hierarchy design, and reliability analysis. His work on Eyeriss and other accelerators has shaped energy-efficient neural network hardware. Recent projects explore hierarchical structured sparsity (HSS) and compute-in-memory (CIM) techniques. Key awards include the ISCA Best Paper Session (2024), IEEE Micro Top Picks (2024), and the SIGMICRO Test of Time Award (2022). He co-advises students with Prof. Vivienne Sze, focusing on sparse tensor acceleration and energy-efficient designs. Awards: 2023 IEEE Rau Award 2022 IASED Lifetime Achievement Award 2020 National Academy of Engineering Membership 2009 Eckert-Mauchly Award Grants and collaborations span industry partnerships (e.g., NVIDIA) and academic initiatives. Emer leads the Emze Group, exploring hardware-software co-design for emerging architectures. Current work includes sparse tensor accelerators (e.g., HighLight, Tailors) and modeling tools like Sparseloop and Accelergy.

David Greavesمشاهده پروفایل

مدرس ارشد

• Computer Architecture
• Programming Languages
• Semantics and Verification
• +۳ مورد دیگر

David Greaves serves as a University Senior Lecturer in the Department of Computer Science and Technology at the University of Cambridge, where he conducts research and teaches undergraduate courses including Databases (Part IA) and Programming in C and C++ (Part IB). His academic work focuses on bridging hardware and software systems through innovative compilation techniques and architectural design. His research spans computer architecture, programming languages, semantics and verification, and systems and networking, with particular emphasis on hardware-software co-design, memory safety mechanisms, and FPGA-based acceleration. Greaves has developed specialized compiler frameworks like Kiwi for translating high-level programs into hardware implementations, and created security models such as FRAMER for capability-based memory protection. Analysis of his recent publications reveals a consistent focus on compiler infrastructure for hardware acceleration, with significant contributions to Bluespec Verilog compilation, dataflow intermediate representations, and cache-friendly security models. His work demonstrates strong interdisciplinary connections between formal methods, hardware design, and systems security, often targeting practical implementations in FPGA environments. Greaves maintains active involvement in hardware description language development and power analysis tools, as evidenced by his contributions to TLM Power and other electronic design automation frameworks. His research approach consistently emphasizes practical toolchain development alongside theoretical foundations.

Arsène Pérard-Gayotمشاهده پروفایل

پژوهشگر ارشد

• Computer Graphics
• Ray Tracing Algorithms
• High-Performance Computing
• +۱ مورد دیگر

Dr. Arsène Pérard-Gayot is a Research Fellow in the Computer Graphics Lab at Saarland University, Germany. His research develops high-performance rendering systems through compiler innovations and hardware optimization techniques. Pérard-Gayot's work creates frameworks for automatic generation of optimized renderers using partial evaluation, eliminating manual compiler development. His FLOWER compiler enables efficient dataflow programming for FPGAs, while Rodent generates specialized renderers for CPUs/GPUs. Additional contributions include ray tracing acceleration structures for irregular grids and BVH traversal abstractions. Publications demonstrate consistent focus on bridging high-level programming models with hardware efficiency. Collaborative projects include molecular dynamics simulation mapping to heterogeneous architectures and distributed ray tracing for massive scenes. Research outcomes advance real-time rendering capabilities and domain-specific compiler technologies for scientific computing.

• Neural Networks
• Hardware-Accelerated Computing
• FPGA Systems
• +۴ مورد دیگر

Walter Stechele is a Professor at the Technical University of Munich (TUM), holding a position in the Department of Integrated Systems within the TUM School of Computation, Information and Technology. His research focuses on hardware-software co-design for neural networks, embedded systems optimization, and edge computing applications. Key areas include FPGA acceleration of convolutional neural networks (CNNs), quantization-aware training, and adversarial robustness in multi-bit networks. He also investigates sensor fusion, automotive imaging systems, and medical image registration techniques. His work bridges theoretical advancements in machine learning with practical deployment challenges on resource-constrained hardware. Notable contributions include methodologies like MATAR (multi-quantization-aware training) and HW-flow-fusion (inter-layer scheduling for CNN accelerators). His research addresses critical issues such as numerical stability in 8-bit Winograd convolutions and optimizing imaging through automotive windshields. Leveraging FPGA platforms, he explores energy-efficient implementations of binarized neural networks (BNNs) for tasks like driveable area detection and gesture recognition on edge devices. His publications frequently emphasize real-world applications in autonomous driving, robotics, and medical imaging, demonstrating a commitment to translating algorithmic innovations into deployable systems.

Erik P. de Vinkمشاهده پروفایل

دانشیار

• Formal Methods
• Software Product Lines
• Probabilistic Systems
• +۶ مورد دیگر

Erik P. de Vink is an Associate Professor at Eindhoven University of Technology (TU/e), Department of Mathematics and Computer Science. He also serves as an Associated Research Fellow at CWI, the Dutch National Research Institute for Mathematics and Computer Science. His research focuses on formal methods, software product lines, dynamic system adaptation, and probabilistic process algebra. He has held roles such as Treasurer of Formal Methods Europe and organized symposia like the International Symposium on Formal Methods (2018). His academic background includes a PhD from VU Amsterdam, a Senior Researcher position at KPN, and prior teaching at Leiden University. Key research interests include formal modeling of software systems using tools like mCRL2 and Prism, analysis of feature-behavior interactions in software product lines, and validation techniques for dynamic system adaptation. He has co-promoted 9 PhD students in areas like denotational semantics, security, and probabilistic process algebra. His work integrates theoretical computer science with practical applications in distributed systems and concurrency. Recent articles explore topics such as formal methods education, bisimulation in polyhedral models, and probabilistic process analysis. He contributes to open-source tool development (e.g., mCRL2) and has published extensively in journals like Formal Aspects of Computing and Journal of Logical and Algebraic Methods in Programming .

Maciej Bestaمشاهده پروفایل

پژوهشگر

• Sparse Graph Computations
• Large Language Models
• Graph Neural Networks
• +۷ مورد دیگر

Maciej Besta is a leading researcher at ETH Zurich's Institute for Computing Platforms, where he heads research initiatives at the Scalable Parallel Computing Lab (SPCL) and contributes to the ETH Future Computing Laboratory (EFCL). Working under the mentorship of Professor Torsten Hoefler, he has established himself as a prominent figure in high-performance computing, graph processing, and large language models. Position: Researcher at Institute for Computing Platforms, ETH Zurich Research Leadership: Head of Sparse Graph Computations and Large Language Models Research at SPCL Collaboration: Leads project management for SPCL's contributions to ETH Future Computing Laboratory Besta's research spans multiple abstraction levels, from hardware and network topologies to middleware, algorithms, and programming models. His primary focus areas include graph-enhanced language models, graph neural networks, graph databases, and sparse models, with applications across various computational settings. He approaches these problems through rigorous performance modeling and formal reasoning, emphasizing both scalability and practical implementation. His recent publications reveal a clear trend toward integrating graph structures with language models and AI systems. Besta has pioneered work on graph databases, knowledge graphs of thoughts, and higher-order graph neural networks, while maintaining his strong foundation in high-performance computing and network topology design. His research bridges traditional HPC with cutting-edge AI, creating novel approaches for efficient large-scale computation. IEEE TCSC Award for Excellence in Scalable Computing (Early Career, 2023) Multiple Best Paper Awards at Supercomputing conferences (2022, 2023) ACM SIGHPC Doctoral Dissertation Award (2022) ETH Medal for outstanding doctoral thesis (2021) Fellow of The Explorers Club (2022) Besta actively mentors ETH Zurich students through semester projects, Bachelor's, and Master's theses, focusing on graph processing and related computer science challenges. His mentorship extends beyond technical guidance, incorporating lessons from his extensive polar and mountaineering expeditions that emphasize mental resilience, efficient risk management, and leadership. He has supervised numerous student projects that have resulted in high-impact publications at top-tier conferences. As a core member of the Scalable Parallel Computing Lab, Besta collaborates with researchers across ETH Zurich and international institutions. His unique approach integrates insights from extreme environment expeditions into research methodology, creating a distinctive framework for tackling complex computational problems. The lab's work under his leadership spans theoretical modeling, practical implementation, and real-world deployment of high-performance systems.

Kunle Olukotunمشاهده پروفایل

استاد

• Computer Architecture
• Parallel Programming
• Chip Multiprocessors
• +۴ مورد دیگر

Kunle Olukotun is a Professor of Electrical Engineering and Computer Science at Stanford University's School of Engineering, where he has been faculty since 1991. He directs the Stanford Pervasive Parallelism Lab (PPL) and co-leads the Transactional Coherence and Consistency (TCC) project. His research focuses on computer architecture, parallel programming environments, and scalable parallel systems. Key areas include chip multiprocessors (CMPs), transactional memory systems, domain-specific languages (DSLs) for heterogeneous computing, and hardware-software co-design for machine learning workloads. His work bridges theoretical foundations with practical systems implementation. Notable contributions include the Stanford Hydra research project (one of the first chip multiprocessors with thread-level speculation), founding Afara Websystems (acquired by Sun Microsystems), and developing the Niagara processor architecture. His DSL frameworks like Green-Marl and Spatial enable efficient graph analysis and hardware acceleration. His publications reveal strong trends in parallel systems evolution: from foundational CMP research (2000s) to transactional memory (2004-2010), then DSLs for heterogeneous computing (2010-2015), and currently foundation model systems (2023-2025). Subfield analysis shows consistent focus on hardware-software co-design, sparse computation, and compiler techniques across decades. ACM Fellow (2006) for contributions to multiprocessors on a chip and multi-threaded processor design Best Paper Award at IEEE International Symposium on Workload Characteristics (IISWC '10) for EigenBench Olukotun actively mentors researchers through the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate parallelism across application domains. His projects have secured significant industry partnerships, including the acquisition of his startup Afara Websystems by Sun Microsystems. Current research focuses on compiler frameworks for foundation model systems and hardware acceleration for sparse machine learning workloads, supported by collaborations with major tech companies. He leads the Stanford Pervasive Parallelism Lab (PPL), which develops compiler and runtime systems for heterogeneous architectures. The lab's work spans DSLs, hardware acceleration, and parallel programming models, with strong industry ties to companies like NVIDIA and Google. Current initiatives include the Mosaic compiler framework and Stardust architecture for sparse tensor computation.