Joel S. Emer

Joel S. Emer is a Professor of the Practice in MIT's Department of Electrical Engineering and Computer Science (EECS) and a Senior Distinguished Research Scientist at NVIDIA. His research focuses on computer architecture, processor micro-architecture, and performance modeling. He has contributed to advancements in simultaneous multithreading, cache optimization, and reliability analysis. Emer holds over 25 patents and has published over 60 papers, earning awards like the IEEE Rau Award and induction into the National Academy of Engineering.

• Education:
  • Ph.D., Electrical Engineering, University of Illinois Urbana-Champaign, 1979
  • M.S., Electrical Engineering, Purdue University, 1975
  • B.S., Electrical Engineering, Purdue University, 1974 (highest honors)

Research interests include accelerator architectures for sparse computation and deep learning, spatial processing, memory hierarchy design, and reliability analysis. His work on Eyeriss and other accelerators has shaped energy-efficient neural network hardware. Recent projects explore hierarchical structured sparsity (HSS) and compute-in-memory (CIM) techniques.

Key awards include the ISCA Best Paper Session (2024), IEEE Micro Top Picks (2024), and the SIGMICRO Test of Time Award (2022). He co-advises students with Prof. Vivienne Sze, focusing on sparse tensor acceleration and energy-efficient designs.

• Awards:
  • 2023 IEEE Rau Award
  • 2022 IASED Lifetime Achievement Award
  • 2020 National Academy of Engineering Membership
  • 2009 Eckert-Mauchly Award

Grants and collaborations span industry partnerships (e.g., NVIDIA) and academic initiatives. Emer leads the Emze Group, exploring hardware-software co-design for emerging architectures. Current work includes sparse tensor accelerators (e.g., HighLight, Tailors) and modeling tools like Sparseloop and Accelergy.