Daniel Sanchez

Dr. Daniel Sanchez is a Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (MIT), where he leads the Computation Structures Group within the Computer Science and Artificial Intelligence Laboratory (CSAIL). His research focuses on computer architecture, scalable systems, and memory hierarchies, with particular emphasis on multicore and many-core systems, quality-of-service guarantees, and runtime systems.

Education:

• Ph.D. in Electrical Engineering, Stanford University (2012)
• M.S. in Electrical Engineering, Stanford University (2009)
• B.S. in Telecommunications Engineering, Technical University of Madrid (UPM) (2007)

Research Interests: Dr. Sanchez’s work spans computer architecture innovations such as cache partitioning (KPart), software-defined caches (Jenga), and accelerators for sparse computing (Azul, Terminus). He designs systems that enhance performance, energy efficiency, and scalability in modern computing environments. His projects include the Swarm Architecture for ordered parallelism and architectures supporting fully homomorphic encryption.

Articles Trends: Recent publications emphasize accelerators for sparse algorithms, cryptographic hardware (e.g., Fully Homomorphic Encryption), and high-performance computing. His work bridges hardware-software co-design to tackle challenges in irregular applications, memory hierarchies, and secure computing.

Awards & Grants: No scientific awards explicitly listed, but his work has been recognized in top conferences (e.g., MICRO, ISCA).

Advising & Teaching: He advises over 20 Ph.D. and master’s students, including current advisees Axel Feldmann and Hyun Ryong Lee. He teaches courses like 6.5900 Computer System Architecture and 6.191 Computation Structures at MIT.

Labs & Teams: Leader of the Computation Structures Group at MIT CSAIL, collaborating with researchers like Joel Emer, Srini Devadas, and Armando Solar-Lezama. His team explores cutting-edge architectures and systems for next-generation computing.