Keith D. Cooper is the L. John and Ann H. Doerr Professor in Computational Engineering and Professor of Computer Science at Rice University. He holds a courtesy appointment in the Department of Electrical and Computer Engineering. His research focuses on program analysis, optimization, and compiler construction. He has authored influential textbooks like Engineering a Compiler and has produced 18 Ph.D. students. Cooper has served in key administrative roles, including Chair of Computational and Applied Mathematics (2019–2020), Associate Dean for Research in the Brown School of Engineering (2012–2018), and Co-Director of the Ken Kennedy Institute for Information Technology (2015–2019). Education: Ph.D. (1983), M.A. (1982), and B.S. (1978) in Mathematical Sciences and Electrical Engineering from Rice University. Research Interests: Program analysis and optimization, compiler design, parallel computing, adaptive compilation, and memory hierarchy optimization. His work includes foundational contributions to interprocedural analysis, register allocation (Chaitin-Briggs algorithm), and compiler frameworks like ParaScope. Awards: ACM Fellow, George R. Brown Award for Superior Teaching (2019), and the L. John and Ann H. Doerr Chair (2019). Grants & Leadership: Played a pivotal role in Rice’s Data Science Initiative and the design of Duncan Hall. Advised over 25 students and contributed to numerous grants in compiler research and high-performance computing. Labs & Teams: Key contributor to the Rice Compiler Group and the Ken Kennedy Institute, advancing research in compilers, parallel computing, and computational science.
Assoc Prof Anupam Chattopadhyay is an Associate Professor in the College of Computing & Data Science at Nanyang Technological University (NTU), Singapore. He also holds a courtesy appointment in the School of Physical & Mathematical Sciences. His research focuses on computer architecture, security, design automation, and quantum computing. Anupam received his PhD from RWTH Aachen University in 2008, followed by roles at CoWare R&D and RWTH Aachen as a Junior Professor before joining NTU in 2014. Education: B.E., Jadavpur University, India MSc, ALaRI, Switzerland PhD, RWTH Aachen University, Germany Research Interests: Anupam’s work spans quantum computing, hardware security, AI security, post-quantum cryptography, and emerging technologies. His contributions include novel high-level synthesis techniques for cryptography, reliability estimation flows for embedded processors, and exploration of coarse-grained reconfigurable architectures. His research has been featured in major outlets like The Economist and Asian Scientist. Awards: Borcher's plaque (2008) for outstanding doctoral dissertation Nomination for Best IP Award (ACM/IEEE DATE 2016) Nomination for Best Paper Award (International Conference on VLSI Design 2018) Advising & Grants: Anupam leads a team of over 20 researchers, overseeing projects funded by various grants. He has advised numerous doctoral students and collaborates with institutions like Temasek Labs and the Indian Statistical Institute. Labs & Teams: His research group focuses on advanced topics in secure computing, quantum-resistant systems, and hardware-software co-design, leveraging cutting-edge tools and platforms for next-generation technologies.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and the founder and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research and Technology – Hellas (FORTH) in Heraklion, Crete, Greece. He has held academic positions since 1986 and played a pivotal role in establishing the Computer Science Department at the University of Crete. His research spans computer architecture, interconnection networks, VLSI systems, and high-performance computing, with a strong focus on scalable, low-power, manycore systems and RISC-V. He has led numerous European R&D initiatives, including serving as Coordinator of the ExaNeSt project. PhD in Computer Science, University of California, Berkeley (1983) MSc in Electrical Engineering and Computer Science, University of California, Berkeley (1980) Diploma of Electrical Engineering, National Technical University of Athens (1978) Manolis Katevenis's research focuses on advancing scalable system architectures for high-performance and big data computing. His work in computer architecture includes RISC-V, exascale computing, and manycore systems. He has made foundational contributions to interprocessor communication, particularly through remote-write, remote-DMA, and remote-enqueue mechanisms, and has pioneered innovations in interconnection networks and low-latency network interfaces. His research integrates hardware and software co-design to optimize performance, energy efficiency, and scalability in large-scale computing systems. The recent publications highlight a strong trend in exascale computing, interconnection networks, and FPGA-based prototyping of manycore systems. His work emphasizes scalable, low-power architectures, with recurring themes in congestion management, fair scheduling, crossbar design, and hardware-software integration for HPC. The articles span high-impact journals such as IEEE/ACM Transactions on Networking, IEEE Micro, and Computer Networks, reflecting sustained contributions to computer architecture and networking. ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981–1983) Greek State Fellowship (1973–1978) Stelios Pichoridis Award for Outstanding University Teaching (2015) Member of Academia Europaea (elected 2012) Award by the Secretary General of the Region of Crete (2003) IEEE Milestone recognition for the RISC Project (2015) Manolis Katevenis has supervised over 50 graduate theses and mentored many prominent Greek computer architects, including recipients of the ACM Maurice Wilkes Award. He has served as Principal Investigator or co-PI in over 30 R&D projects with a total budget exceeding 18 million euros, including major European initiatives such as ExaNeSt (which he coordinated), EuroEXA, EcoScale, SARC, ENCORE, and multiple HiPEAC Network of Excellence projects. His leadership extends to project coordination, architectural design, FPGA prototyping, and systems software development. Katevenis founded and leads the CARV Laboratory at FORTH-ICS, a major research team with 80–100 members focused on computer architecture and VLSI systems. The lab has spun off the Distributed Computing Systems (DCS) Laboratory and is central to European exascale computing efforts, including participation in the European Processor Initiative. CARV has developed large-scale prototypes such as the 768-core ExaNeSt system and the Formic FPGA platform for manycore research.
Andrew B. Kahng is a Distinguished Professor of Computer Science & Engineering and Electrical and Computer Engineering at the University of California San Diego. He leads research in VLSI physical design, AI-driven chip design, and semiconductor roadmapping. His work focuses on advancing EDA tools, such as the OpenROAD Project and TILOS AI Institute, to address challenges in chip design automation. He has authored over 500 publications, holds 35 patents, and is a Fellow of both ACM and IEEE. His accolades include the 2019 Ho-Am Prize in Engineering. Key affiliations include the VLSI CAD Laboratory and leadership roles in international conferences like DAC and ISPD. Kahng has mentored numerous students, contributing to their academic and professional success. His research spans from foundational algorithms (e.g., placement and routing) to industry collaboration through initiatives like the OpenROAD Project, which provides open-source tools for chip design. Recent advancements include ML integration in EDA, pathfinding frameworks (PROBE3.0), and contributions to the semiconductor technology roadmap. His work emphasizes open-source ecosystems and interdisciplinary collaboration to drive innovation in microelectronics.
M. Hassan Najafi is an Assistant Professor in the Department of Electrical, Computer, and Systems Engineering at Case School of Engineering, Case Western Reserve University. His research focuses on emerging digital design methodologies, stochastic and unary computing, hyperdimensional computing, edge computing, and low-power VLSI design. He holds a PhD in Electrical Engineering from the University of Minnesota (2018), an M.S. in Computer Architecture from the University of Tehran (2014), and a B.S. in Computer Engineering (Hardware specialization) from the University of Isfahan (2006). Education: PhD Electrical Engineering, University of Minnesota, 2018 M.S. Computer Architecture, University of Tehran, 2014 B.S. Computer Engineering (Hardware), University of Isfahan, 2006 His research interests span artificial intelligence, computer architecture, and machine learning , with a focus on energy-efficient computing systems. He explores novel paradigms like hyperdimensional computing and processing-in-memory to advance edge computing applications. His work aims to bridge theoretical innovations with practical hardware implementations. Dr. Najafi has received prestigious awards including the NSF CAREER Award (2024), GLSVLSI Best Paper Awards (2023-2024), and the DAC Outstanding Dissertation Award (2018). He holds the Lockheed Martin Corporation Endowed Professorship (2023) and the ULL Francis Patrick Clark/BORSF Professorship (2022). His professional affiliations include Senior Member status in IEEE. While specific grants and advising details are not detailed here, his work emphasizes interdisciplinary collaboration in hardware-software co-design for next-generation computing systems.
Christos Papachristou, PhD is a Professor in the Department of Electrical, Computer, and Systems Engineering at the Case School of Engineering , Case Western Reserve University. His academic career spans over four decades since earning his PhD in Electrical Engineering & Computer Science from Johns Hopkins University in 1975. Prof. Papachristou's research focuses on Embedded Systems Design , Quantum Computing Architectures , Reconfigurable Systems/FPGAs , and Hardware Security . His work addresses critical challenges in fault-tolerant systems , secure system design , and high-level synthesis . Notable contributions include innovations in radiation-hardened SRAM designs , hardware trojan detection , and quantum computing infrastructure . Key Achievements: Recipient of the Albert Nelson Marquis Lifetime Achievement Award (2019) IEEE Best Paper Award for Cognitive Communications for Aerospace Applications (2019) Invited NATO Summer School Lecturer (2008) in Spain/UK and Cleveland His publications reflect expertise in circuit reliability , embedded system security , and quantum computing . Recent work emphasizes electromigration mitigation and reconfigurable architecture kernels . Prof. Papachristou collaborates extensively on projects funded by NSF, DoD, and industry partners. Teaching specialties include Parallel Computer Architectures , Configurable Devices , and Quantum Computing , reflecting his dual focus on theoretical innovation and practical implementation in advanced technologies.
Anastasija Collen is a Lecturer at the Research Institute for Statistics and Information Science at the University of Geneva . She holds a Ph.D. from the same institution and specializes in cybersecurity, IoT security, and automotive systems. Her work focuses on developing secure architectures, cryptographic protocols, and regulatory frameworks for connected and automated vehicles. Her research spans Automotive cybersecurity standards and certifications Trust modeling in distributed networks Blockchain applications for IoT security Human-centric risk visualization Data privacy compliance (GDPR) Recent publications emphasize secure automotive systems , including trusted platform modules (TPM), lightweight cryptographic protocols (LOKI-2), and certification roadmaps. She also explores IoT security through frameworks like anomaly-based intrusion detection and blockchain-enhanced defense mechanisms. Collen’s work has been presented at conferences such as IEEE ICCP , ARES , and IEEE EuroS&PW , with over 40 peer-reviewed articles since 2018. She maintains an active presence on ResearchGate and Google Scholar .
Thibaut Vandervelden is a Researcher at Vrije Universiteit Brussel's Faculty of Engineering, Department of Electronics and Informatics. His work focuses on hardware security, embedded systems, and cryptographic implementations for resource-constrained environments. With an h-index of 4, he has produced significant research output since 2019, primarily in Sensors, IEEE Access, and Future Generation Computer Systems. His research interests center on practical security implementations for IoT devices and embedded systems, with particular expertise in Rust programming for secure embedded development, cryptographic protocol optimization, and network security for low-power wireless networks. His work bridges theoretical security concepts with practical implementation challenges in constrained environments. Analysis of his recent publications reveals a strong trend toward secure embedded systems development, with increasing focus on Rust programming language applications, zero-knowledge proofs for privacy-preserving systems, and optimization of cryptographic operations for IoT devices. His research demonstrates consistent collaboration with colleagues including Ruben De Smet, An Braeken, and Kris Steenhaut. Scientific recognition includes: IACR RWC'21 Cryptohackathon on Functional Encryption: 2nd prize (2021) Vandervelden actively participates in research community building through organizing workshops like RustIEC and presenting at events focused on embedded systems security. His work has been referenced in Wikipedia pages and garnered attention across academic and professional platforms, with media contributions on cybersecurity research in Flanders. He leads and participates in research teams focused on wireless community development and the Internet of Batteryless Things, contributing to both theoretical frameworks and practical implementations in hardware security.
Dr. Teresa Maria Canavarro Menéres Mendes de Almeida is an Assistant Professor at the Department of Electrical and Computer Engineering, Instituto Superior Técnico (University of Lisbon), and a researcher at INESC-ID. She specializes in circuit theory, signal processing, and biosensor technologies. Her teaching focuses on core electrical engineering courses such as Circuit Analysis, Analog/Digital Filters, and Electronics fundamentals, for which she has received multiple teaching excellence awards from the IST Pedagogical Council (2013-2019). Her research interests span resistive circuits, magnetoresistive biosensors, and biochip-based microsystems. She has developed educational materials like problem sets and lecture slides on filters and circuits, alongside applied work in biomedical embedded systems and sensor modeling. Collaborations include projects on portable biosensing platforms and noise analysis in biochip elements. Notable achievements include a series of teaching excellence awards highlighted for courses like 'Circuit Theory and Fundamentals of Electronics' and 'Analog and Digital Filters.' Her work bridges theoretical circuit analysis with practical applications in biomedical engineering and digital signal processing.
Ralf Kundel is a Professor of Computer Science at the University of Applied Sciences Darmstadt, Germany. He holds a Ph.D. (2022) and dual M.Sc./B.Sc. degrees (2015-2017) from TU Darmstadt. His research focuses on network programmability, hardware acceleration using FPGAs and P4-programmable switches, Quality of Service (QoS), Time Sensitive Networking (TSN), and Network Intrusion Detection Systems (NIDS). He leads the Adaptive Communication Group (ACS) since 2021, emphasizing network data plane programmability. Key projects include BMWK's Real Lab Drive 4.0 (TSN in industrial networks), Deutsche Telekom's Dynamic Networks (SDN and FPGA-based carrier networks), and BMBF initiatives like Open 6G Hub (disaggregated O-RAN architectures) and AI-NET-PROTECT (machine learning for network security). He contributed to open-source frameworks like P4-UPF (5G UPF implementation), P4-CoDel (AQM), and P4STA (network testing). Publications span over 25 peer-reviewed works and five patent applications, with recent focus on high-performance network evaluation and programmable hardware applications.
Louis-Noël Pouchet is an Associate Professor in the Department of Computer Science at Colorado State University, with a joint appointment in the Electrical and Computer Engineering department. He leads research in high-performance computing, focusing on polyhedral compilation, performance portability, and hardware-software co-design. His research interests include polyhedral compilation, iterative and adaptive compilation, machine learning for compilers, performance-oriented domain-specific languages, energy-aware program optimization, and high-level synthesis. He develops compiler technologies to optimize and parallelize code for heterogeneous platforms, with applications in scientific computing and embedded systems. The 15 most recent publications highlight a strong focus on compiler optimization for high-performance systems, particularly using the polyhedral model. Key themes include data locality, parallelization, vectorization, memory access optimization, and performance modeling. His work spans both theoretical advances in program transformation and practical implementations in tools like PoCC and PolyOpt. Member, Center for Domain-Specific Computing (NSF) Member, DSL Technology for Exascale Computing (DoE) Lead, Polyhedral Compilation Research (NSF and Intel ISRA) Former member, Platform-Aware Compilation Environment (DARPA) He teaches courses on polyhedral compilation and has developed widely used software tools such as PoCC, PolyBench/C, and PolyOpt/C. His research is supported by major funding agencies including NSF, DoE, and Intel.
Robert Stewart is a Professor in the Department of Electronic and Electrical Engineering at the University of Strathclyde, where he leads the 20-member StrathSDR engineering team. His research focuses on software-defined radio (SDR), dynamic spectrum access, FPGA-based implementations, and next-generation 5G private networks. He has played a pivotal role in major UK 5G testbed projects such as 5GRuralFirst, 5G NewThinking, and 5GRailNext, with a strong emphasis on rural and underground rail connectivity. His expertise spans digital signal processing, shared spectrum systems, and RFSoC-based designs. He was a founding partner of the Scotland 5G Centre in 2019 and co-founded Steepest Ascent Ltd, later acquired by MathWorks. He previously held the Xilinx Professor of DSP and Digital Logic chair and served as Head of Department (2014–2017) and Director of the Institute for Sensors, Signals and Communications. His recent publications (2024–2025) highlight advancements in intelligent resource management for shared spectrum networks, FPGA-based beamforming, 5G transmitter design on RFSoC platforms, and deep learning for modulation classification. These works reflect a strong integration of machine learning, hardware acceleration, and next-generation wireless systems. UCLA Extension Distinguished Professor Award 2010 Award for Digital Inclusion (2019) Xilinx Professor of Signal Processing (2006–2013) Stewart has led numerous EPSRC and industry-funded research projects and actively collaborates with AMD, MathWorks, and Cisco. He supervises research students and contributes to datasets and open-source tools. He also delivers technical short courses for industry professionals on RFSoC and PYNQ platforms. He has led the StrathSDR team in developing innovative solutions for private 5G networks and spectrum sharing, contributing to both academic knowledge and industrial applications through the Scotland 5G Centre and Neutral Wireless Ltd.
Marco Guarnieri is an Associate Professor at IMDEA Software Institute in Madrid, Spain. His research focuses on the design, analysis, and implementation of practical systems for securely storing and processing sensitive data, with particular emphasis on security at the hardware-software boundary and microarchitectural attacks and defenses. Guarnieri received his PhD in Computer Science in 2017 from ETH Zurich's Institute of Information Security, following an MSc (2012) and BSc (2010) in Computer Engineering from Università degli Studi di Bergamo. His research spans security and privacy, program verification, programming languages, and formal methods. Guarnieri's work has particularly focused on addressing vulnerabilities related to speculative execution (Spectre attacks), side-channel analysis, hardware-software security interfaces, and leakage contracts. His approach often combines formal verification techniques with practical system implementation to develop robust security solutions. Guarnieri's publications reveal a strong focus on microarchitectural security, with recent work addressing secure speculation countermeasures, compiler security guarantees against Spectre attacks, side-channel security of cryptographic implementations, and hardware-software leakage contracts. His research shows a progression from database security early in his career to the hardware-software security boundary that characterizes his current work. Among his notable achievements are a Best Paper Award at CCS 2024 and Distinguished Paper Awards at CCS 2023 and CCS 2022. His paper 'Hardware-Software Contracts for Secure Speculation' also received a Best Paper Award. Guarnieri actively contributes to the academic community through program committee roles, including the PriSC Steering Committee, and has organized events such as PLMW@PLDI 2023. He is seeking talented researchers (interns, PhD students, and postdocs) to join his group at IMDEA Software Institute to work on security at the hardware-software interface.
Dr. Lars Schütze is a researcher at the Chair for Compiler Construction within the Faculty of Computer Science at Dresden University of Technology (TU Dresden). Holding a PhD in Computer Science from TU Dresden, he currently serves as a PostDoc specializing in domain-specific compilers for verifiable Full Homomorphic Encryption (vFHE) and hybrid quantum-classical computing systems. His academic credentials from TU Dresden include: Bachelor's degree in Computer Science Master's degree in Computer Science PhD in Computer Science (awarded February 2025) Schütze's research centers on advanced compiler design for emerging computational paradigms. His foundational work explores context-oriented and role-based programming languages, focusing on runtime optimization and dispatch mechanisms. Recent efforts pivot toward post-quantum security through homomorphic encryption compilers and hybrid quantum-classical computing frameworks. His research bridges theoretical language design with practical compiler implementation, emphasizing verifiable security and performance efficiency in next-generation computing environments. Publication analysis reveals a clear evolution from context-oriented programming (2017-2020) toward cryptographic compiler development (2022-2025). Early work optimized role-based dispatch systems, while recent publications establish compiler frameworks for Fully Homomorphic Encryption using MLIR infrastructure. His research consistently addresses performance bottlenecks in dynamic language features while transitioning toward quantum-resistant cryptography solutions. Scientific Awards: No awards documented in source materials Dr. Schütze supervises student theses in Homomorphic Encryption and Quantum-Classical Computing frameworks, offering projects spanning Bachelor to Master levels. His research is funded through institutional projects including (verifiable) Full Homomorphic Encryption and Hybrid Quantum-Classical Computation, though specific grant details remain undisclosed. He actively develops compiler infrastructure for encrypted computation and quantum-classical orchestration. As core personnel in TU Dresden's Chair for Compiler Construction, Schütze contributes to the RoSI project (role-based software infrastructures) and leads current initiatives in vFHE. His team collaborates on building domain-specific compiler toolchains that address quantum computing threats through post-quantum cryptographic solutions while advancing hybrid execution models for emerging hardware architectures.
Fabio Dovis is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, and a member of the Interdepartmental Center PIC4SeR (PoliTO Interdepartmental Center for Service Robotics). His career spans multiple decades with significant contributions to Global Navigation Satellite Systems (GNSS) research and applications. Dr. Dovis serves on the Steering Committee of the Institute of Navigation (2021-2023) and is an Editorial Board member of GPS SOLUTIONS since 2017. His research focuses on satellite navigation technologies with applications spanning from environmental monitoring to space exploration. He leads the Navigation, Signal Analysis and Simulation (NavSAS) Research Group, which is actively developing innovative GNSS solutions. His research portfolio includes satellite navigation receiver design, GNSS for environmental and atmospheric monitoring, GNSS positioning security, and applications in service robotics and precision agriculture. His work bridges theoretical advancements with practical implementations across diverse domains, from terrestrial navigation systems to lunar exploration. Dr. Dovis has supervised numerous PhD students working on cutting-edge GNSS research, with current students focusing on areas such as lunar navigation, GNSS interference monitoring, and robust positioning solutions for challenging environments. His research spans multiple EU-funded projects including EMERITUS (2022-2025), LuGRE (2021-2025), and ROOT (2020-2022). Steering Committee member - Institute Of Navigation, USA (2021-2023) Editorial Board member - GPS SOLUTIONS (2017-) Program chair - International Conference on Localization and GNSS 2013 He has contributed to numerous patents in GNSS technology and serves as Scientific Director for multiple research initiatives including the NODES program under the PNRR framework. His recent publications demonstrate a strong focus on advancing GNSS capabilities for space exploration, particularly for lunar missions, as well as addressing critical challenges in GNSS security and reliability.
