جستجوی استاد راهنمای دانشگاهی

Sebastian Maierمشاهده پروفایل

پژوهشگر

• Distributed Systems
• Operating Systems
• Many-Core Architectures
• +۳ مورد دیگر

Sebastian Maier is a Researcher at the Department of Computer Science 4 (Distributed Systems and Operating Systems) at Friedrich-Alexander-University Erlangen-Nuremberg, part of the Faculty of Engineering. His work focuses on invasive computing, many-core architectures, and distributed systems. He has contributed to projects like the iRTSS (Invasive Run-Time Support System) and the OctoPOS kernel, emphasizing system software for resource arbitration and latency-aware systems. Maier has taught courses such as System-level Programming in C and Operating Systems exercises from 2013 to 2019. His research interests include hardware-software co-design, embedded systems security, and runtime systems for future architectures. He has advised students on thesis topics like distributed TCP/IP stacks and asynchronous communication interfaces in many-core systems. His recent work explores dynamic hardware-managed queues (DySHARQ) and resource arbitration mechanisms for tile-based architectures. These efforts aim to optimize parallel processing and real-time performance in embedded systems. Maier has also collaborated on latency-aware operating systems (LAOS) and security in embedded systems (SESES). Key Projects: iRTSS, AAM (Asynchronous Abstract Machines), SHARQ, LAOS Lab/Teams: Part of the Invasive Computing SFB/TRR 89 project (Project C1) His publications span conferences like ROME, ROSS, and HiPEAC, addressing challenges in many-core kernel design, scalability, and hardware-accelerated systems. Current research trends focus on adapting system software to heterogeneous and dynamic many-core environments.

• Electronic Design Automation
• Fault Injection Simulation
• RISC-V Processors
• +۷ مورد دیگر

Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors. University: Technical University of Munich Department: Chair of Design Automation Email: johannes.geier@tum.de Research Interests Electronic Design Automation (EDA) for analog and digital circuits Fault tolerance and reliability in RISC-V architectures Security analysis of post-quantum cryptographic systems Timing analysis and microfabrication techniques Optical Networks-on-Chip (NoC) and emerging technologies Compiler-assisted hardware security implementations Recent Research Trends Specializes in fault injection methodologies for hardware security validation Develops open-source tools like vRTLmod for RTL simulation acceleration Explores RISC-V vector extensions for post-quantum cryptography Investigates differential fault effect equivalence checks for efficiency Designs compiler-based security countermeasures against instruction skip attacks Works on concurrent multi-node XCP proxy server architectures

Oliver Mischkeمشاهده پروفایل

پژوهشگر

• Side-Channel Cryptanalysis
• Efficient Cryptographic Implementation
• Hardware Security
• +۳ مورد دیگر

Dr. Oliver Mischke is an academic researcher focusing on hardware security and cryptographic implementations. He was affiliated with the Chair for Embedded Security at the Horst Görtz Institute for IT Security, Ruhr-University Bochum. His research emphasizes side-channel cryptanalysis, efficient cryptographic algorithms, and secure hardware design. Mischke completed his PhD in Security in Information Technology at Ruhr-University Bochum (2011–2013), with a year abroad at Purdue University (2007–2008). He has held roles as a Security Engineer (ESCRYPT GmbH) and an intern at Qualcomm's Product Security Group. His research interests include FPGA-based cryptographic implementations, fault analysis, and countermeasures against side-channel attacks. Notable contributions involve dynamic logic reconfiguration for FPGA security, glitch-resistant masking schemes, and evaluation of AES countermeasures. Mischke's publications span conferences like HOST, CHES, and IEEE venues, focusing on cryptographic hardware security, timing attacks, and secure embedded systems. His work bridges theoretical cryptography with practical hardware implementations, addressing vulnerabilities in reconfigurable and embedded systems. He has contributed to projects such as the MicroACP crypto-processor and IPSec core designs. His collaborations include prominent institutions and industry partners, reflecting a strong emphasis on applied security solutions.

Akash Kumarمشاهده پروفایل

استاد

• Embedded Systems
• Processor Design
• Energy-Efficient Computing
• +۷ مورد دیگر

Akash Kumar is a Professor and holds the Chair of Embedded Systems at the Faculty of Electrical Engineering and Information Technology, Ruhr University Bochum, a position he has held since April 1, 2024. He previously served as Professor for Processor Design at the Technical University of Dresden from 2015 to 2024 and was an Assistant Professor at the National University of Singapore from 2011 to 2015. His research focuses on advancing embedded systems through innovative hardware design. Key areas include reconfigurable circuits using silicon nanowires, approximate computing for energy efficiency, and enhancing hardware security by obscuring task execution from external observation. His work targets applications in autonomous vehicles, AI, and consumer electronics where computational efficiency and privacy are critical. Akash Kumar’s research demonstrates a clear trend toward minimizing energy consumption and hardware footprint while maintaining functional adequacy, particularly in safety- and resource-constrained environments. His work bridges computer architecture, electronic design automation, and AI-driven embedded applications. Scientific Awards: No awards mentioned in the text. Advising and Grants: The text does not provide information about students or research grants. However, given his leadership of a research chair and extensive international collaborations, it is likely he supervises a research team and secures competitive funding, though specifics are not available. Labs and Teams: He leads a research team at Ruhr University Bochum focused on embedded systems, working on silicon nanowires, reconfigurable hardware, and approximate computing. The team’s work emphasizes both performance optimization and system security.

• Information Security
• Cryptographic Protocols
• Web Security
• +۷ مورد دیگر

Tim Würtele is a Ph.D. researcher at the Institute of Information Security at the University of Stuttgart. His work focuses on formal security analysis of cryptographic protocols, particularly those underpinning critical web standards like OAuth 2.0, OpenID Connect, FAPI, ACME, and Web Payment APIs. He has contributed to identifying and mitigating vulnerabilities in these protocols, collaborating with standardization bodies such as the OpenID Foundation and W3C. University of Stuttgart Würtele's research interests include web security , cryptographic protocol verification , and formal methods for analyzing real-world implementations. His work addresses both theoretical and practical security flaws in protocols used by billions of users globally, spanning high-risk sectors like open banking and healthcare. He has published extensively in top-tier venues such as IEEE S&P, CCS, and ESORICS, often uncovering critical vulnerabilities and proposing formally verified fixes. In 2025, Würtele co-authored a paper introducing audience injection attacks , a novel class of vulnerabilities in Web-based authentication standards. His 2024 publications focused on fixing and verifying the FAPI 2.0 protocol , while 2023 papers addressed GNAP and layered protocol analysis . Earlier works (2021–2022) scrutinized the ACME certificate management standard and W3C Web Payment APIs , revealing over-charge vulnerabilities and formalizing security guarantees.

Christian Dietrichمشاهده پروفایل

استاد

• Operating Systems
• Real-Time Systems
• Embedded Systems
• +۵ مورد دیگر

Christian Dietrich is a Professor at Technische Universität Braunschweig, specializing in operating systems, real-time systems, and software dependability. Previously affiliated with Friedrich-Alexander-Universität Erlangen-Nürnberg and Leibniz Universität Hannover, he leads the Systems Research and Architecture (SRA) group. His research focuses on dependable embedded operating systems, fault tolerance, static analysis, and compiler optimization. He has contributed to projects like dOSEK, cHash, and MELF, addressing challenges in real-time scheduling, redundancy reduction, and variability management in system software. Education: PhD in Computer Science from Leibniz Universität Hannover (2019). Research Interests: Embedded systems dependability, real-time OS design, static/dynamic analysis, fault injection, and compiler-driven optimization. His work bridges theory and practice, with applications in automotive and safety-critical systems. Recent Work: Recent articles explore compiler caching efficiency (IRHash), memory management (HyperAlloc), and fault-space pruning for hardware fault injection. His work on cHash reduced redundant compilations by 80%, earning a USENIX ATC Best Paper Award. Awards: ECRTS 2018 Outstanding Paper, RTAS 2015 Best Paper, and multiple teaching accolades. Supervised over 30 theses, including topics like live patching, fault injection frameworks, and stack-sharing mechanisms. Lab/Team: Heads the SRA group, collaborating on projects like AHA (Hardware Abstraction), CLASSY-FI (fault injection), and CADOS (RTOS variability management). Active in conferences like OSDI, EuroSys, and RTSS.

• High-Performance Computing
• Parallel Computing
• Power Management
• +۳ مورد دیگر

Barry Rountree is a researcher affiliated with Lawrence Livermore National Laboratory (LLNL), specializing in High-Performance Computing (HPC), Power Management, and Parallel Computing. His work focuses on optimizing energy efficiency, fault tolerance, and performance in large-scale supercomputing environments. He has contributed extensively to the development of tools and frameworks for power-aware scheduling, hardware overprovisioning, and visualization performance optimization. Key research interests include HPC system design, processor manufacturing variability, and energy-efficient algorithms. Rountree has collaborated with institutions like NERSC and Intel on projects involving exascale computing challenges and resource management strategies. His publications span conferences such as SC, IPDPS, and ICS, emphasizing practical solutions for scalable and sustainable HPC systems. Notable contributions include the SpackNVD vulnerability audit tool, the msr-genie framework for processor register navigation, and adaptive power management strategies for visualization applications. His work highlights interdisciplinary approaches to addressing computational challenges in science and engineering domains.

Hans-Joachim Wunderlichمشاهده پروفایل

استاد

• Computer Architecture
• Hardware Reliability
• Fault Tolerance
• +۷ مورد دیگر

Prof. Hans-Joachim Wunderlich is a Professor at the University of Stuttgart's Institute of Computer Architecture and Computer Engineering, within the Faculty of Computer Science, Electrical Engineering, and Information Technology. His research focuses on hardware reliability, fault tolerance, and testing methodologies for VLSI circuits and embedded systems. He specializes in areas such as delay fault testing under PVT variability, approximate communication, and aging-aware design. Key research interests include robust testing techniques for small delay faults, error-tolerant communication protocols (e.g., RAPPER and Gray code-based approaches), and GPU-accelerated simulation of faults. His work addresses challenges in functional safety, interconnect reliability, and securing reconfigurable architectures against security violations. He explores energy-efficient iterative solvers for approximate computing environments and develops methods for predicting device aging and early life failures. Prof. Wunderlich’s contributions span academic and industrial applications, with a focus on real-time systems and dependable multi-processor systems-on-chip (MPSoCs). His research integrates formal verification, machine learning for defect detection, and hybrid protection schemes for reconfigurable scan networks. Recent work emphasizes stress-aware testing strategies and optimization of sensor data streaming in resource-constrained environments.

Benedict Herzogمشاهده پروفایل

پژوهشگر

• Energy-Efficient Systems
• Operating Systems
• Embedded Systems
• +۳ مورد دیگر

Benedict Herzog is a Researcher at the Bochum Operating Systems and System Software (BOSS) group at Ruhr-Universität Bochum (RUB). Previously, he was part of the Department of Computer Science 4 (Distributed Systems and Operating Systems) at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU). His work focuses on energy-efficient systems, operating systems optimization, and embedded computing. Herzog holds a Master's degree in Computer Science from FAU, where his thesis explored energy demand estimation using artificial neural networks, and a Bachelor's degree in Energy-aware error correction in wireless sensor networks. His research interests span energy-aware computing, system software design, and machine learning applications for optimizing edge and embedded systems. He actively participates in academic activities, serving as a reviewer for conferences like TECS, SBESC, and EMSOFT. Herzog has taught courses such as 'Systemnahe Programmierung in C' and 'Energy-Aware Computing Systems' at FAU, and advised multiple students on topics ranging from interrupt handling overhead to Meltdown/Spectre mitigation impacts. Key technical contributions include frameworks for energy measurement integration (EnergyBudgets), system-call aggregation (AnyCall), and automated OS configuration optimization. His work bridges hardware-software co-design challenges in energy efficiency, with applications in edge computing and real-time systems.

Marco Guarnieriمشاهده پروفایل

دانشیار

• Security and Privacy
• Program Verification
• Programming Languages
• +۳ مورد دیگر

Marco Guarnieri is an Associate Professor at IMDEA Software Institute in Madrid, Spain. His research focuses on the design, analysis, and implementation of practical systems for securely storing and processing sensitive data, with particular emphasis on security at the hardware-software boundary and microarchitectural attacks and defenses. Guarnieri received his PhD in Computer Science in 2017 from ETH Zurich's Institute of Information Security, following an MSc (2012) and BSc (2010) in Computer Engineering from Università degli Studi di Bergamo. His research spans security and privacy, program verification, programming languages, and formal methods. Guarnieri's work has particularly focused on addressing vulnerabilities related to speculative execution (Spectre attacks), side-channel analysis, hardware-software security interfaces, and leakage contracts. His approach often combines formal verification techniques with practical system implementation to develop robust security solutions. Guarnieri's publications reveal a strong focus on microarchitectural security, with recent work addressing secure speculation countermeasures, compiler security guarantees against Spectre attacks, side-channel security of cryptographic implementations, and hardware-software leakage contracts. His research shows a progression from database security early in his career to the hardware-software security boundary that characterizes his current work. Among his notable achievements are a Best Paper Award at CCS 2024 and Distinguished Paper Awards at CCS 2023 and CCS 2022. His paper 'Hardware-Software Contracts for Secure Speculation' also received a Best Paper Award. Guarnieri actively contributes to the academic community through program committee roles, including the PriSC Steering Committee, and has organized events such as PLMW@PLDI 2023. He is seeking talented researchers (interns, PhD students, and postdocs) to join his group at IMDEA Software Institute to work on security at the hardware-software interface.

Joachim Falkمشاهده پروفایل

پژوهشگر

• Electronic System Level Design
• Hardware-Software Co-Design
• Data-Flow Graphs
• +۶ مورد دیگر

Joachim Falk is a researcher at the Department of Hardware-Software Co-Design (Computer Science 12) at Friedrich Alexander University Erlangen-Nuremberg. With over 20 years of experience since joining the department in 2004, he specializes in electronic system level design, dataflow programming, and hardware-software co-design, contributing significantly to the field through publications, teaching, and research leadership. His educational background includes: Doctorate degree (Dr.-Ing.) in Computer Science from FAU (2014) Diploma degree in electrical engineering (data processing) from Georg-Simon-Ohm University of Applied Science Nuremberg (2002) Falk's research focuses on Electronic System Level Design, Hardware/Software Code Generation for Data-Flow Graphs, Compiler Optimizations, and Parallel Architectures. His work bridges theoretical computer science with practical embedded systems implementation, particularly through the SystemC framework and his contributions to the SysteMoC language. He actively explores energy-efficient computing approaches for dataflow networks and embedded systems, with recent work emphasizing self-powering networks, clock and power gating techniques, and multi-reader buffer implementations for heterogeneous architectures. His recent publication trends reveal a consistent focus on optimizing dataflow networks for energy efficiency and performance. Key themes include self-powering dataflow networks, innovative clock and power management techniques, buffer management strategies for heterogeneous many-core systems, and invasive computing approaches. His research demonstrates a strong connection between theoretical models and practical implementation challenges in embedded systems design. Dr. Falk teaches courses including 'Entwicklung interaktiver eingebetteter Systeme' (Development of Interactive Embedded Systems) for Winter Semester 2024/2025 and 'SystemC' for Summer Semester 2024, supervising multiple theses on security modeling at the electronic system level and sleep/wake-up strategies for hardware implementations of dataflow networks. His research is conducted within the framework of projects like SysteMoC (representation of computational models in SystemC) and SystemCoDesigner (design space exploration for embedded systems).

• System-level Security
• Multi-Processor System-on-Chip Protection
• Network-based Security
• +۵ مورد دیگر

Johanna Sepulveda is a Lecturer at the Chair of Information Security , Technical University of Munich (TUM). She has over 12 years of experience in embedded security design, focusing on innovative protection techniques against side-channel and fault attacks, as well as hardware/software development for System-on-Chip (SoC) and Multi-Processor System-on-Chip (MPSoC) systems. Education: M.Sc. and Ph.D. in Electrical Engineering – Microelectronics from the University of São Paulo, Brazil Key Research Areas: System-level Security, MPSoC Protection, Post-Quantum Cryptography, Side-channel Attacks, and Network-on-Chip Security Contact: johanna.sepulveda@tum.de Her research emphasizes secure communication structures, quality-of-service in network-based systems, and verification of embedded security implementations. She has held postdoctoral and visiting researcher positions at institutions including the University of Lyon, University of South Brittany, and University of Bremen.

• Computer Science
• Embedded Systems
• Neuromorphic Engineering
• +۳ مورد دیگر

Nikil D. Dutt is a Professor in the Department of Computer Science at the University of California, Irvine. His research focuses on embedded systems, neuromorphic engineering, healthcare informatics, and machine learning applications. He holds a Ph.D. in Computer Science from the University of Illinois Urbana-Champaign (1989). His work spans interdisciplinary areas such as neuromorphic computing, wearable healthcare systems, and energy-efficient architectures. Notable contributions include frameworks for self-aware systems, neuromorphic hardware design, and data-driven healthcare solutions. He collaborates extensively with researchers in computer architecture, biomedical engineering, and cyber-physical systems. Recent publications highlight advancements in EEG analysis for traumatic brain injury, energy-efficient machine learning on wearables, and secure embedded systems for automotive applications. His research integrates theoretical models with practical implementations, addressing challenges in reliability, scalability, and adaptability.

• Hardware Trojan Design
• Netlist Reverse Engineering
• Neuro Engineering
• +۲ مورد دیگر

Alexander Hepp serves as a Lecturer at the Chair of Security in Information Technology, Technical University of Munich (TUM), where he contributes to both teaching and cutting-edge hardware security research. His current teaching responsibilities include C++ Lab, Embedded Systems and Security, and Strategic Management for Engineers, where he acts as primary lecturer for the latter course. His research centers on hardware trojan design/identification and netlist reverse engineering within the chair's broader security initiatives. His research portfolio demonstrates deep specialization in hardware security vulnerabilities, with emphasis on hardware trojan insertion/detection methodologies and reverse engineering countermeasures. Recent work explores neuro engineering applications and RISC-V-based security implementations, often leveraging open-source hardware frameworks. His publications reveal consistent innovation in hardware obfuscation techniques and netlist analysis tools, addressing critical gaps in pre-silicon security validation. His 12 publications from 2021-2024 show strong focus on hardware security conferences like DATE and DDECS, with recurring themes in trojan detection, reverse engineering challenges, and cryptographic hardware validation. The research trajectory indicates growing emphasis on practical countermeasures against physical attacks and standardized vulnerability assessment frameworks. Scientific Awards: Best Paper Award at DDECS 2022 for 'Hardware Obfuscation of Digital FIR Filters' No verifiable information exists regarding student advising or grant funding in available sources. He operates within Prof. Sigl's research ecosystem which actively pursues projects in fault attacks, IoT security, physical unclonable functions, and post-quantum cryptography implementations, with recent work emphasizing hardware reverse engineering challenges in advanced semiconductor designs.

• Secure Computation
• Privacy-Preserving Machine Learning
• Homomorphic Encryption
• +۴ مورد دیگر

M. Sadegh Riazi is an Assistant Professor in the Department of Computer Science and Engineering at the University of California, San Diego's Jacobs School of Engineering. He completed his PhD at UCSD in 2020 with a dissertation titled 'Towards A Private New World: Algorithm, Protocol, and Hardware Co-Design for Large-Scale Secure Computation.' Dr. Riazi's research focuses on the critical intersection of cryptography, machine learning, and hardware security, with particular emphasis on making secure computation practical for real-world applications. His work spans secure multi-party computation, homomorphic encryption, privacy-preserving machine learning, and hardware acceleration for cryptographic protocols. He has made significant contributions to optimizing secure computation frameworks for deep learning applications, developing techniques that balance security guarantees with computational efficiency. His publication record shows a clear progression from foundational secure computation techniques to increasingly sophisticated applications in privacy-preserving AI. Notably, his work on HEAX (Homomorphic Encryption Acceleration) and XONN (XNOR-based Oblivious Neural Network) demonstrates practical approaches to making encrypted deep learning feasible. The research trends in his publications indicate a consistent focus on bridging theoretical cryptographic security with practical system implementations. Dr. Riazi has established a strong collaborative network, most prominently with Professor Farinaz Koushanfar's research group at UCSD, with whom he has co-authored numerous papers across multiple domains including biometric security, secure hardware design, and privacy-preserving machine learning. His research has been published in top-tier venues including IEEE Security & Privacy, USENIX Security, ASPLOS, and CCS, reflecting the high impact and quality of his work in both the security and systems communities.