Johannes Geier

Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors.

• University: Technical University of Munich
• Department: Chair of Design Automation
• Email: johannes.geier@tum.de

Research Interests

• Electronic Design Automation (EDA) for analog and digital circuits
• Fault tolerance and reliability in RISC-V architectures
• Security analysis of post-quantum cryptographic systems
• Timing analysis and microfabrication techniques
• Optical Networks-on-Chip (NoC) and emerging technologies
• Compiler-assisted hardware security implementations

Recent Research Trends

• Specializes in fault injection methodologies for hardware security validation
• Develops open-source tools like vRTLmod for RTL simulation acceleration
• Explores RISC-V vector extensions for post-quantum cryptography
• Investigates differential fault effect equivalence checks for efficiency
• Designs compiler-based security countermeasures against instruction skip attacks
• Works on concurrent multi-node XCP proxy server architectures