جستجوی استاد راهنمای دانشگاهی

Andrea Bastoniمشاهده پروفایل

پژوهشگر ارشد

• Real-Time Systems
• Cyber-Physical Systems
• Operating System Design
• +۵ مورد دیگر

Dr. Andrea Bastoni is a Postdoctoral Researcher and Research Fellow at the Chair of Cyber-Physical Systems in Production Engineering at Technical University of Munich (TUM), Faculty of Mechanical Engineering. He is also the CTO and co-founder of Minerva Systems , developing operating system solutions for AI-ready embedded applications. His expertise spans real-time operating systems, cyber-physical systems, and predictable system design for heterogeneous platforms. His research focuses on enhancing predictability of memory hierarchies in complex SoCs through techniques like memory bandwidth regulation and cache partitioning. This work has industrial applications in safety-critical domains such as avionics and railways, where he contributes to certifiable hypervisors and operating systems. As former Software Architect of the PikeOS hypervisor at SYSGO GmbH (2012-2020), he specialized in DO-178C, IEC 61508, and EN 50128 standards. His academic background includes a Ph.D. in Computer Engineering from the University of Rome Tor Vergata (2007-2011), where he developed LITMUS^RT as part of UNC's Real-Time Systems Group during a visiting researcher period (2009-2010). His publications reflect ongoing work on Multicore Real-Time Scheduling , Mixed-Criticality Task Isolation, and Arm DynamIQ shared unit analysis. He actively participates in program committees for conferences like RTSS, DSN, and DATE.

Daniel Großeمشاهده پروفایل

استاد

• Formal Verification
• Hardware Verification
• Electronic Design Automation
• +۳ مورد دیگر

Prof. Daniel Große serves as Professor at the Institute for Complex Systems (ICS) within Johannes Kepler University Linz, Austria, while maintaining a dual affiliation with the German Research Center for Artificial Intelligence (DFKI) in Bremen. His research centers on Electronic Design Automation (EDA), specializing in verification, debugging, and synthesis of complex hardware/software systems through advanced virtual prototyping techniques. His primary research domains include Formal Verification , Hardware Verification , and Virtual Prototyping , with significant contributions to RISC-V architecture development and embedded systems validation. Current projects like PaSVer (automotive electronics), AUTOASSERT (analog-digital verification), and VerSys (RISC-V software platforms) demonstrate his focus on bridging simulation and formal methods for safety-critical applications. Recent publications reveal accelerating trends in metamorphic testing for embedded graphics libraries and RISC-V vector extensions, alongside innovations in waveform analysis tools like Surfer. His work increasingly integrates AI-assisted verification while maintaining rigorous formal methods foundations. Prof. Große actively supervises student research, having guided Lucas Klemmer's PhD thesis and nine Bachelor theses on topics ranging from RISC-V processor design to transaction visualization. His projects including SATiSFy (autonomous vehicle security) and CONVERS (complex system design automation) secure substantial research funding from academic and industry partners. He leads the Institute for Complex Systems' development of open-source tools such as RISC-V VP++ and contributes to international standards through program committee roles at DATE, ICCAD, and RISC-V Summit Europe.

• Embedded Systems
• Hardware-Software Co-Design
• Invasive Computing
• +۷ مورد دیگر

Prof. Dr.-Ing. Jürgen Teich is a full Professor and Chair for Hardware-Software Co-Design at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU). He serves as Head of Department Computer Science and Vice Dean of the Technical Faculty since August 2024, and has been Speaker of the FAU Research Center Embedded System Initiative (FAU ESI) since 2023. His educational background includes: Diploma degree in Electrical Engineering, University of Kaiserslautern (1989) Dr.-Ing. degree in Electrical Engineering, University of Saarland (1993) Habilitation (PD Dr.-Ing.) entitled "Synthesis and Optimization of Digital Hardware/Software Systems" (1996) Prof. Teich's research focuses on Embedded Systems , Invasive Computing , Hardware-Software Co-Design , and Reconfigurable Computing . His work spans from theoretical foundations to practical implementations, with particular emphasis on resource-constrained systems, many-core architectures, and energy-efficient computing. He has pioneered research in invasive computing paradigms that enable more efficient use of many-core processors by allowing applications to dynamically claim resources. His recent publications reveal a strong trend toward energy-efficient AI deployment on embedded devices , security of embedded systems , and novel memory technologies . There's a clear focus on practical implementations of machine learning on microcontrollers (TinyML), hardware acceleration for data processing, and innovative approaches to power management in self-powered systems. Among his notable scientific awards are: IEEE Fellow (since 2018) Member of Academia Europaea, Section Informatics (since 2011) Member of the National Academy of Science and Engineering (acatech) (since 2018) Member of the German Society of Humboldtians (since 2021) Prof. Teich has been Principal Investigator for numerous DFG-funded projects including SFB/Transregio 89 "Invasive Computing" (2010-2022), SFB 694, and multiple priority programs. He has coordinated large collaborative research efforts across Germany and internationally, with significant funding from DFG and other sources. His research group has produced influential work in embedded systems design and co-design methodologies. He leads the Hardware-Software Co-Design research group at FAU, which focuses on innovative approaches to embedded system design, invasive computing architectures, and efficient implementation of machine learning on resource-constrained devices. The group maintains strong collaborations with industry partners including Intel, Xilinx, and automotive companies.

Dominique Devrieseمشاهده پروفایل

استاد

• Functional Programming
• Object Capabilities
• Secure Compilation
• +۵ مورد دیگر

Dominique Devriese is a professor at the Department of Computer Science, KU Leuven, and a member of the DistriNet research group. His work bridges computer security, programming languages, and formal verification. Research interests: Functional Programming, Object Capabilities, Secure Compilation, Dependently-typed Programming, Modal Type Theory Teaching: Formal Systems, Object-Oriented Programming, CyberSecurity, Secure Software His research focuses on rigorous software systems security through capability machines and secure compilation techniques. He actively contributes to formal verification using Agda and Haskell, with recent work on multimode type theory and effect parametricity. Key publication trends include: multimode/presheaf type theory, capability-based security models, formal verification of hardware/software abstractions, and parametricity applications in programming languages. Contact: Email: dominique.devriese@kuleuven.be ORCID: 0000-0002-3862-6856

Daniel Müller-Gritschnederمشاهده پروفایل

استاد مدعو

• TinyML
• Embedded Software Development
• Soft Error Resilience
• +۴ مورد دیگر

Daniel Müller-Gritschneder is an Adjunct Teaching Professor (Privatdozent) at the Technical University of Munich (TUM), affiliated with the Chair of Electronic Design Automation. He leads the 'Electronic System Level' research group, focusing on embedded systems, TinyML, virtual prototyping, and hardware resilience. He temporarily served as head of the Chair of Real-Time Systems (2019–2020) and holds a senior membership in IEEE. His research spans: TinyML : Optimizing neural network inference for microcontrollers. Virtual Prototyping : Fast simulation for embedded software development (e.g., ETISS simulator). Runtime Verification : Hardware monitoring for safety-critical systems. Fault Tolerance : Cross-layer resilience against soft errors. Design Automation : NoC synthesis and RISC-V toolchain optimization. His publications emphasize RISC-V-based systems, TinyML deployment, fault injection, and embedded AI. Recent works show trends toward compiler-assisted security, thermal management, and automated design-space exploration for edge devices. Awards: Best Paper Award (SiPS 2019) Habilitation Award (Bund der Freunde der TUM, 2019) 2nd Best Paper (SMACD'15) Best Paper nominations at DAC'07, DATE'10, Analog'10, NOCS'13 He advises researchers in the Electronic System Level group and contributes to EU projects (e.g., Scale4Edge). His lab develops tools like ETISS, MLonMCU, and Seal5 for RISC-V and TinyML ecosystems.

Marc Reichenbachمشاهده پروفایل

استاد

• Integrated Circuits
• Embedded Systems
• VLSI Design
• +۷ مورد دیگر

Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.

Peter Sewellمشاهده پروفایل

استاد

• Concurrency
• Programming Languages
• Formal Methods
• +۵ مورد دیگر

Peter Sewell is Professor of Computer Science at the University of Cambridge Computer Laboratory, where he builds rigorous foundations for real-world computer systems to enhance robustness, security, and formal verification of hardware-software interactions. His educational background includes undergraduate studies at the University of Cambridge and University of Oxford, followed by a PhD from the University of Edinburgh in 1995 under Robin Milner's supervision. Professor Sewell's research focuses on concurrency models (x86, ARM, Power, C/C++11), verified compilation, formal semantics for C/linking/filesystems/TLS, and applied semantics tools. He pioneers executable ISA specifications through projects like Sail and Cerberus, addressing relaxed-memory concurrency and capability-based security architectures. His 2020-2026 publications reveal a clear trajectory toward formal verification of hardware security properties, with increasing emphasis on capability systems (Arm Morello, CHERI) and real-world applicability of concurrency models across ARM, RISC-V, and MIPS architectures. Scientific recognition: Royal Society University Research Fellowship (1999-2007) He leads major research initiatives in systems security formalization, supported by Cambridge positions and collaborative projects with industry partners. His work bridges theoretical formal methods and practical systems engineering through executable semantics frameworks. As a core member of Cambridge's Systems Research Group, he directs projects including Sail (ISA semantics), Cerberus (C semantics), and verification frameworks for capability architectures, fostering interdisciplinary collaboration across hardware and software security domains.

• Embedded Systems
• Compilers
• Hardware-Software Co-Design
• +۵ مورد دیگر

Prof. Dr. rer. nat. Rainer Leupers is a faculty member at RWTH Aachen University, chairing the Department of Software for Systems on Silicon. His research focuses on embedded systems, hardware-software co-design, virtual prototyping, and security in computing-in-memory architectures. He has published extensively on RRAM accelerators, logic locking, and neuromorphic security. Chair of Software for Systems on Silicon Research in hardware security and deep learning accelerators Recent publications on cross-tool virtual frameworks and thermal side-channel attacks His work bridges system-level modeling with practical security implementations, emphasizing reliability and performance in heterogeneous computing environments. Key trends in his 2025-2023 articles include compute-in-memory optimization, neural network inference efficiency, and security vulnerabilities in emerging hardware. Awards and formal recognitions are not explicitly detailed in the provided materials. He has not directly mentioned advising students or research grants in the given text fragments. The chair's contact information includes an office at ICT Cube 1, Electrical Engineering, Aachen, with direct email and website links.

• Information Security
• Cybersecurity
• Smart Card Security
• +۱۵ مورد دیگر

Konstantinos Markantonakis is a Professor of Information Security in the Department of Information Security at Royal Holloway, University of London, where he also serves as Director of the Smart Card and IoT Security Centre and the Transformative Digital Technologies, Security and Society Catalyst. He is a leading figure in embedded systems and IoT security, with extensive research and consultancy experience. BSc (Hons) in Computer Science, Lancaster University, 1995 MSc in Information Security, Royal Holloway, 1996 PhD in Smart Card Security, Royal Holloway, 2000 MBA in International Management, Royal Holloway, 2005 His research focuses on securing embedded and cyber-physical systems, including smart cards, mobile devices, drones, automotive systems, and IoT. He investigates trusted execution environments, side-channel analysis, secure protocols, and hardware-software binding. His work bridges theoretical security and practical implementation, often uncovering zero-day vulnerabilities in consumer devices. The recent publications highlight a strong trend in trusted computing, remote attestation, secure embedded systems, and privacy-preserving technologies. His research integrates blockchain for secure energy trading, develops frameworks for edge machine learning, and advances forensic techniques for damaged storage media. He also explores covert channels in mobile and cloud environments, demonstrating a deep understanding of both offensive and defensive security. Best Paper Award Markantonakis has led major research projects such as EXFILES (forensic extraction from encrypted smartphones), Future TPM (quantum-resistant trusted modules), and the Academic Centre of Excellence in Cyber Security Research. He has supervised numerous PhD students and delivered keynotes at international conferences. His consultancy work has impacted financial institutions, transport operators, and mobile platform security. He leads the Smart Card and IoT Security Centre, a research hub focusing on practical security for connected devices. The centre conducts cutting-edge research in side-channel attacks, secure application execution, and forensic analysis, contributing significantly to both academic and industrial advancements in cybersecurity.

• Electronic Design Automation (EDA)
• Computer Architecture
• Embedded Systems
• +۵ مورد دیگر

Prof. Wolfgang Ecker is a Professor at the Technical University of Munich (TUM), affiliated with the Chair of Design Automation within the TUM School of Computation, Information and Technology . His research focuses on Electronic Design Automation (EDA), RISC-V processor architectures, and hardware-software co-design. He leads projects advancing EDA tools for embedded systems, neural network acceleration, and formal verification methodologies. Ecker's work bridges machine learning techniques with traditional EDA challenges, addressing topics like energy-efficient AI inference and automated documentation generation. His contributions span compiler optimization, FPGA implementations, and fault analysis in digital systems. Recent research highlights include contributions to the TRISTAN project for RISC-V ecosystem development, model-driven architecture frameworks, and AI-driven timing analysis. He actively collaborates on open-source EDA tools and explores Rust-based embedded systems development. Ecker’s lab emphasizes practical applications in edge computing and automotive microcontroller safety, with a strong emphasis on interdisciplinary collaboration across TUM’s CIT School. His publications (15 most recent listed) reflect a focus on EDA tool innovation, processor design, and leveraging machine learning for hardware optimization. While no specific awards are mentioned, his involvement in ERC-funded projects and leadership in international collaborations underscores his academic impact.

Batuhan Sesliمشاهده پروفایل

پژوهشگر

• Embedded Systems
• Machine Learning Hardware Acceleration
• RISC-V Architecture
• +۳ مورد دیگر

Batuhan Sesli is a Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design) at Friedrich-Alexander University Erlangen-Nuremberg (FAU), Germany, since July 2024. His work focuses on embedded systems with emphasis on hardware acceleration for machine learning and efficient deployment of TinyML applications on resource-constrained devices. His educational background includes: M.Sc. in Information and Communication Technology from FAU (2022-2024) B.Sc. in Electrical & Electronics Engineering from Istanbul Ozyegin University, Turkey, with a minor in Computer Science (2016-2021) Research interests span acceleration techniques for machine learning workloads via RISC-V ISA extensions and specialized hardware accelerators, efficient deployment of TinyML on low-power devices, and co-design of AI algorithms and hardware. His work optimizes the synergy between algorithmic requirements and hardware capabilities in embedded systems, targeting practical solutions for edge AI applications. His recent DATE 2024 publication on DNN acceleration through weight clustering on RISC-V custom functional units exemplifies the trend toward energy-efficient specialized hardware, reflecting his focus on bridging algorithmic demands with hardware constraints in real-world embedded scenarios. He teaches a tutorial on Embedded Systems for Winter Semester 2024/2025 and offers thesis opportunities in his research domain, though no current open theses are listed.

• Computer Architecture
• Hardware Design
• Signal Processing
• +۷ مورد دیگر

Prof. Dr.-Ing. Holger Blume serves as Vice President for Research and Transfer at Leibniz University Hannover while maintaining his academic position as Professor in the Architectures and Systems Section within the Faculty of Electrical Engineering and Computer Science. He holds multiple leadership positions including Chairperson of the Research Commission and Central Ethics Committee, Executive Board member of eNIFE (Leibniz Research Initiative for Neurosciences), and membership in both the Laboratory of Nano and Quantum Engineering and L3S Research Centre. His research interests span computer architecture, hardware design, signal processing, AI accelerators, hearing aid technology, and biomedical engineering. His work bridges theoretical computer science with practical applications in automotive systems, medical devices, and quantum engineering. Professor Blume's research demonstrates strong interdisciplinary connections between electrical engineering, computer science, and biomedical applications, with particular emphasis on hardware-oriented solutions for real-world problems. Analysis of his recent publications (2023-2025) reveals a strong focus on hardware acceleration for AI and signal processing applications, particularly in automotive radar/LiDAR systems and hearing aid technology. His work shows consistent innovation in RISC-V processor design, specialized hardware for mathematical functions, and biomedical applications of engineering principles. The research demonstrates a clear trajectory toward energy-efficient, specialized computing architectures for specific application domains. As Vice President for Research and Transfer, Professor Blume oversees significant research initiatives at Leibniz University Hannover, which hosts multiple Clusters of Excellence including PhoenixD (Photonics, Optics, and Engineering), QuantumFrontiers, and Hearing4all. The university participates in numerous collaborative research centers and junior research groups funded by DFG, BMBF, and EU programs. Professor Blume is actively involved in multiple research facilities including the Laboratory of Nano and Quantum Engineering and the L3S Research Centre. His work connects with Leibniz University's research focuses on optical technologies, quantum optics and gravitational physics, and biomedical research and technology. His leadership positions indicate strong involvement in shaping the research strategy and ethical framework of the university's scientific endeavors.

• Computer Architecture
• Parallel Processing
• FPGA Design
• +۳ مورد دیگر

Frank Hannig is a Professor at the University of Erlangen-Nuremberg, Germany, specializing in computer architecture and high-performance computing. His research focuses on FPGA acceleration, hardware-software co-design, neural network optimization, and embedded systems. He has collaborated extensively with co-authors such as Jürgen Teich and Oliver Reiche, producing over 200 publications since 2001. His work emphasizes domain-specific languages (DSLs) for image processing (e.g., Hipacc) and compiler optimizations for FPGAs. Key contributions include techniques for quantized neural networks on microcontrollers, CGRA toolchain evaluation, and efficient mapping of CNNs onto processor arrays. Hannig also explores energy-efficient architectures and reconfigurable computing for emerging applications like edge AI and automotive systems. Publications span conferences like ASAP, FPL, and ARC, reflecting his interdisciplinary approach to bridging algorithm design and hardware implementation. His research often addresses practical challenges in deploying machine learning models on resource-constrained devices while maintaining performance and energy efficiency.

• Electronic Design Automation
• Fault Injection Simulation
• RISC-V Processors
• +۷ مورد دیگر

Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors. University: Technical University of Munich Department: Chair of Design Automation Email: johannes.geier@tum.de Research Interests Electronic Design Automation (EDA) for analog and digital circuits Fault tolerance and reliability in RISC-V architectures Security analysis of post-quantum cryptographic systems Timing analysis and microfabrication techniques Optical Networks-on-Chip (NoC) and emerging technologies Compiler-assisted hardware security implementations Recent Research Trends Specializes in fault injection methodologies for hardware security validation Develops open-source tools like vRTLmod for RTL simulation acceleration Explores RISC-V vector extensions for post-quantum cryptography Investigates differential fault effect equivalence checks for efficiency Designs compiler-based security countermeasures against instruction skip attacks Works on concurrent multi-node XCP proxy server architectures

Christoph Lüthمشاهده پروفایل

استاد

• Advanced Systems Engineering
• Program Correctness
• Formal Methods
• +۵ مورد دیگر

Christoph Lüth is a Professor of Computer Science at the University of Bremen and Deputy Head of the Cyber-Physical Systems research group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. He has been affiliated with DFKI since 2006 and focuses on constructing provably correct software through theoretical foundations and practical tool development. Doctorate from University of Edinburgh Habilitation from University of Bremen His research spans advanced systems engineering , formal methods , and functional programming , with applications in robotics and hardware security. Recent work emphasizes open-source chip design , post-quantum cryptography , and memory protection for RISC-V architectures . Lüth contributes to projects like PROTECT (cybersecurity resilience), EASEPROFIT (post-quantum secure protocols), DI-OCDCPro (open-source chip design education), and SIGN-HEP (hardware security modules). He has authored over eighty scientific papers. At the University of Bremen, he teaches courses on functional programming , programming languages , and formal methods .