جست‌وجوی استاد و پژوهشگر

• High-Performance Computing
• Reconfigurable Computing
• FPGA Acceleration
• +۷ مورد دیگر

Carlos Alvarez Martinez is a faculty member at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture at the Barcelona School of Informatics (FIB). He is a key member of the Programming Models (PM) research group and collaborates closely with the Barcelona Supercomputing Center (BSC). His research focuses on high-performance computing, FPGA acceleration, task-based programming models like OmpSs, and hardware-software co-design for heterogeneous systems. His research interests center on advancing parallel computing through innovative programming models and hardware acceleration. He investigates efficient task scheduling, resource management in multicore and FPGA-based systems, and runtime support for dataflow models. His work enables high-performance execution of complex applications in domains such as scientific computing and cyber-physical systems. He actively contributes to European initiatives like TEXTAROSSA and AXIOM, aiming to develop next-generation exascale supercomputing technologies. The trend in his recent publications shows a strong focus on leveraging FPGAs for HPC, optimizing SpMV operations, improving task scheduling with hardware support, and developing frameworks for multi-FPGA clusters. His work consistently bridges theoretical models with practical implementations, emphasizing performance, scalability, and energy efficiency in heterogeneous computing environments. Scientific Awards: Premi UPC al Compromís Social 2019 Premi Disseny per al Reciclatge 2013 Alvarez Martinez has advised or collaborated with several doctoral students, including Jaume Bosch, Xubin Tan, and Fahimeh Yazdanpanah. He has been involved in numerous competitive R&D projects, often related to high-performance computing and parallel programming models. His work includes significant contributions to educational innovation, particularly in active learning methodologies and formative assessment using interactive systems. He leads and participates in research labs and teams focused on programming models and computer architecture, notably the PM group at UPC/BSC. These teams develop runtime systems, compilers, and hardware accelerators to push the boundaries of parallel computing efficiency and programmability.

• Space Systems Engineering
• Computer Architecture
• Embedded Systems
• +۵ مورد دیگر

Pablo Parra Espada is an Associate Professor at the Department of Automática, University of Alcalá (Spain), affiliated with the Space Research Group (SRG-UAH). He holds a PhD from the University of Alcalá (2012) titled Integración de tecnologías de desarrollo y análisis basadas en componentes bajo un enfoque multi-plataforma , supervised by Dr. Sebastián Sánchez Prieto and Dr. Óscar Rodríguez Polo. His research focuses on space systems engineering , particularly in RISC-V processor design , embedded systems , and model-driven engineering . Key areas include hardware-software co-design for satellite systems, real-time computing, and fault-tolerant architectures. He has contributed to the Solar Orbiter mission through work on the Energetic Particle Detector (EPD) and its on-board software validation. His recent work emphasizes virtualization techniques for LEON processors, FPGA-based digital beamforming , and spaceborne phased array systems . He also explores model-driven approaches for automated configuration of ground support equipment. His interdisciplinary contributions bridge computer architecture with aerospace applications. Prof. Parra Espada has published extensively on topics such as hardware performance monitoring, memory management units for satellites, and system-level verification of space software. His work combines rigorous engineering methodologies with cutting-edge technologies to address challenges in space instrumentation and embedded systems.

Mateo Valero Cortésمشاهده پروفایل

استاد

• Computer Architecture
• High-Performance Computing
• Parallel Computing
• +۳ مورد دیگر

Mateo Valero Cortés is a renowned Professor of Computer Architecture at the Polytechnic University of Catalonia and Director of the Barcelona Supercomputing Center (BSC). He has held academic and leadership roles since 1974, advancing high-performance computing (HPC) and computer architecture research. His work includes pioneering contributions to vector architectures, multithreading, and instruction-level parallelism. Education includes a Telecommunications Engineering degree from the Polytechnic University of Madrid (1974) and a PhD in Telecommunications Engineering from the Polytechnic University of Catalonia (1980). His research spans over 700 publications, focusing on HPC systems, parallel computing, and supercomputing infrastructure. Key research interests include vector processing, super-scalar processors, and task-based programming models. Recent work emphasizes scalable architectures for exascale computing and energy-efficient hardware-software co-design. Notable achievements include the Eckert-Mauchly Prize (highest in computer architecture), Seymour Cray Award, and Charles Babbage Prize. He has led initiatives like the Spanish Supercomputing Network (RES) and PRACE (European HPC partnership). Academic affiliations include the Royal Academy of Engineering of Spain, ACM Fellow, and IEEE Fellow. He has received 13 honorary doctorates and awards such as Mexico’s Order of the Aztec Eagle. Current projects include the Mont-Blanc HPC prototype and ERC-funded research on multi-core chip design. His BSC oversees over 300 researchers and manages MareNostrum supercomputers.

Francesc Moll Echetoمشاهده پروفایل

دانشیار

• Energy Harvesting
• Integrated Circuit Design
• Low Power Electronics
• +۵ مورد دیگر

Francesc Moll Echeto is an Associate Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Departament d'Enginyeria Electrònica and the Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona. He leads the HIPICS research group focused on high-performance integrated circuits and systems design. His expertise spans energy harvesting, low-power electronics, process variability management, and secure circuit design. He coordinates the Doctorat en Enginyeria Electrònica program and has coordinated EU-funded projects like the European Processor Initiative (EPI). Education: M.S. in Physics, Universitat de les Illes Balears, 1991 Ph.D. in Electronic Engineering, Universitat Politècnica de Catalunya, 1995 Research Focus: His work addresses energy-efficient computing, including: - Design of circuits tolerant to manufacturing variability - Energy harvesting from mechanical and RF sources - Secure hardware countermeasures against side-channel attacks - RISC-V architecture implementations in advanced technologies - Edge computing and autonomous sensor systems Grants & Collaborations: Coordinator of R&D projects like 'ARQUITECTURA DE COMPUTADORES DE ALTAS PRESTACIONES' (PID2023-146511NB-I00) Part of the Barcelona Zettascale Lab consortium Collaborations with Barcelona Supercomputing Center and industry partners Awards: HiPEAC Paper Award (2023, 2024) for innovations in vector processing and DNN acceleration Labs/Teams: Leads the HIPICS group and the EFRICS subgroup, collaborating on EU-funded initiatives like the European Processor Initiative. Active in open-source silicon projects (e.g., Sargantana RISC-V processor).

• Computer Architecture
• High-Performance Computing
• Multicore and Manycore Systems
• +۷ مورد دیگر

Miquel Moreto Planas is a Senior Lecturer in the Department of Computer Architecture at the Barcelona School of Informatics, Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing. His academic profile is deeply rooted in computer architecture and high-performance computing, with a strong emphasis on practical and theoretical advancements in multicore systems, memory management, and hardware acceleration. His research interests span a wide range of topics including computer architecture, high-performance computing, multicore and manycore systems, cache and memory management, hardware acceleration for genomics and AI, RISC-V processor design, processing-in-memory, interconnection networks, and real-time systems. These interests are reflected in his extensive publication record and collaborative projects. The most recent articles highlight a significant trend toward interdisciplinary research, particularly the application of advanced computer architecture techniques to bioinformatics and healthcare. Key themes include the acceleration of genomic sequence alignment using novel hardware such as processing-in-memory, the development of benchmarks for ARM-based HPC systems in genomics, and the creation of AI-based 3D decision support tools for neurosurgical applications. His work also continues to advance core computer architecture topics like cache management, power-aware resource allocation in heterogeneous systems, and the design of secure, post-quantum cryptographic hardware based on RISC-V. Fulbright Award 2011 HiPEAC Paper Award HiPEAC Paper Award 2024 HiPEAC Paper Award Moreto has been a principal investigator or key contributor to multiple competitive R&D+i projects, such as the STRATUM project for neurosurgical tools, REDIOH for open hardware, and the Laboratorio Zettaescala de Barcelona. He has advised several doctoral students, including López, G., Kostalampros, I., and Haghi, A., and is a core member of the CAP (High Performance Computing) research group at UPC. His work is characterized by strong collaborations with leading researchers like Mateo Valero, Eduard Ayguadé, and Jesús Labarta, often bridging the gap between UPC and BSC-CNS. His laboratory and team affiliations are centered around the CAP group and the Barcelona Supercomputing Center, where he contributes to cutting-edge research in high-performance and embedded computer architectures. His recent work on the BIMSA accelerator and the STRATUM project demonstrates a clear future direction toward applying high-performance computing solutions to critical problems in genomics and medicine.

• Computer Architecture
• Parallel Processing
• Networking Systems
• +۳ مورد دیگر

Javier Verdu Mula is a Professor at the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya - UPC) and a key researcher at the CRAAX - Centre de Recerca d'Arquitectures Avançades de Xarxes . His work focuses on computer architecture, parallel processing, and networking systems. Fields of Research include RISC-V virtualization, multithreaded processor optimization, and performance analysis of stateful networking applications. Scientific Awards include the BDigital Global Congress (2015) and Wayra Barcelona (2012) recognitions. Collaborations span institutions like Barcelona Supercomputing Center and researchers such as Manuel Alejandro Pajuelo, Mateo Valero Cortes, and Mario Nemirovsky. His recent publications address RISC-V hypervisor extensions, deep packet processing in parallel architectures, and statistical thread assignment models. He also holds patents in hardware virtualization and resource control systems.

Alastair Reidمشاهده پروفایل

پژوهشگر

• formal verification
• security
• functional languages
• +۱ مورد دیگر

Alastair Reid is a researcher at Intel (2021–present) focusing on formal instruction set architecture (ISA) specifications and model checking processor pipelines. His career spans roles at Google Research (2019–2021) developing Rust verification tools, Arm Ltd (2004–2019) working on formal ISA specifications and vectorizing compilers, University of Utah (1998–2004) on component-based operating systems, Yale University (1994–1998) contributing to Haskell functional reactive programming, and University of Glasgow (1988–1994) in formal specification and verification. Ph.D. in Defining interfaces between hardware and software: Quality and performance , Glasgow University M.Sc. in A precise semantics for Ultraloose Specifications , Glasgow University B.Sc., University of Strathclyde His research interests include formal verification, security analysis, functional programming languages (particularly Haskell and Rust), and computer architecture. He has contributed to the development of machine-readable ISA specifications for ARM, RISC-V, and Intel architectures, and worked on symbolic execution tools like KLEE for Rust verification. Key publications include work on RISC-V specification improvements (2024), formal methods for persistent programming (2023), PLARCH workshop contributions on ISA specification (2023), and foundational papers on ARM processor verification with ISA-Formal (2016). His technical blog posts cover topics in symbolic execution, SMT solvers, and practical verification challenges. Contributions to conferences include committee roles in PLDI (2024), PriSC (2024), and workshop organization in formal methods and programming language design.

Xavier Aragones Cerveraمشاهده پروفایل

دانشیار

• Integrated Circuits Design
• RF Systems
• Substrate Noise Analysis
• +۷ مورد دیگر

Xavier Aragones Cervera is an Associate Professor at the Polytechnic University of Catalonia (UPC), affiliated with the Department of Electronic Engineering (Departament d'Enginyeria Electrònica) within the School of Telecommunications Engineering of Barcelona (Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona). His research focuses on high-performance integrated circuits and systems design, particularly addressing substrate noise, RF circuit design, and aging effects in CMOS technologies. He leads the HIPICS (High Performance Integrated Circuits and Systems Design Group) and contributes to the EFRICS (Efficient and Robust Integrated Circuits and Systems) research group. Education: M.S. in Telecommunication Engineering from UPC (1993), Ph.D. in Electronic Engineering from UPC (1997). His work spans over 130 publications, including peer-reviewed articles, conference presentations, and patents. Key research areas include substrate noise analysis, RFIC design, mixed-signal systems, and reliability engineering. He has advised students such as Marc Manel Molina and Juan Felipe Osorio. Collaborations include projects funded by national and European programs, focusing on microelectronics, IoT, and next-generation semiconductor technologies. Publications highlight experimental studies on substrate noise in VCOs/PLLs, aging compensation in amplifiers, and low-power IoT designs. He has contributed to major initiatives like the Cherenkov Telescope Array and RISC-V processor development in advanced FDSOI technology. His work emphasizes bridging theoretical models with practical circuit implementations, addressing emerging challenges in nanoscale CMOS and BEYOND-CMOS technologies.

• Space Instrumentation
• Radiation Detection
• On-Board Data Management Systems
• +۵ مورد دیگر

Sebastián Sánchez Prieto is a Professor at the Department of Automatic Control, Universidad de Alcalá, Spain, affiliated with the Space Research Group (SRG-UAH). He holds a Doctorate from the same institution (1998) with a thesis on cosmic ion telescope control systems. His research focuses on space instrumentation, radiation detection systems, on-board data management, and embedded systems for space applications. He has contributed extensively to the Solar Orbiter mission, working on the Energetic Particle Detector (EPD) instrumentation and software validation. His technical expertise spans FPGA-based signal processing, RISC-V processor architectures, and model-driven engineering for space systems. Notable work includes advancing virtualization techniques for mixed-criticality space systems, digital beamforming architectures, and neural network applications in particle trajectory analysis. Publications emphasize cutting-edge topics like fault-tolerant computing in space environments, adaptive signal processing for space communications, and low-power positioning systems. He actively develops educational frameworks integrating on-board data management concepts across interdisciplinary university curricula. His contributions include over 50 peer-reviewed articles addressing hardware-software co-design, space software verification, and radiation effects mitigation. Current research explores AI-driven approaches for space instrumentation data analysis and next-generation on-board computing solutions.

• High-Performance Computing
• Computer Architecture
• Parallel Computing
• +۷ مورد دیگر

Francisco Fabio Banchelli Gracia is a researcher affiliated with the Universitat Politècnica de Catalunya (UPC), specifically in the Department of Systems, Automation, and Industrial Informatics at the Barcelona School of Informatics (FIB). He is actively involved in high-performance computing (HPC) research and collaborates with the Barcelona Supercomputing Center (BSC). His research interests include high-performance computing, computer architecture, energy efficiency in computing systems, performance analysis of HPC and computational fluid dynamics (CFD) workloads, Arm-based processors (A64FX, ThunderX2), RISC-V, hardware-software co-design, and HPC education for undergraduates. His work bridges industry practices and academic training, particularly in introducing students to real-world HPC environments. The recent publications highlight a strong focus on evaluating emerging HPC architectures such as NVIDIA Grace and Arm-based systems, developing generic performance and efficiency models, benchmarking production CFD codes, and advancing educational methodologies for HPC. His work spans both technical innovation and pedagogical development in the HPC domain. He has contributed to major HPC conferences such as the International Conference on High Performance Computing (HiPC), Platform for Advanced Scientific Computing (PASC), IEEE Cluster, and IEEE/ACM workshops on HPC education. His collaborations are primarily with researchers at UPC and BSC, especially Filippo Mantovani and Marta Garcia Gasulla. Francisco Fabio Banchelli Gracia is actively engaged in research and publication, with no indication of retirement or former status. He advises on HPC education initiatives and participates in collaborative research projects, though specific grants are not detailed in the provided text. He is part of the CAP (High Performance Computing Group) and works within the UPC-BSC ecosystem, contributing to cutting-edge HPC system evaluation and educational outreach.

Jan Reinekeمشاهده پروفایل

استاد

• static analysis
• real-time systems
• computer architecture
• +۱ مورد دیگر

Jan Reineke is a Professor of Computer Science at Saarland University , where he leads research at the intersection of hardware and software. His work focuses on timing-predictable microarchitectures, real-time systems, and hardware-software security contracts. Affiliation: Saarland University (since 2012) Previous: Postdoctoral scholar at UC Berkeley (2009-2011) Research Interests include static program analysis, real-time systems, computer architecture, and hardware-related security issues. His group develops tools like LLVMTA , uops.info , and Spectector for cache analysis, microarchitectural profiling, and speculative execution security. Design of timing-predictable processors (RTSS 2018, RTSS 2019) Exact LRU cache analysis (CAV 2017, POPL 2019, RTSS 2019) Detection of speculative information flows (S&P 2020, S&P 2021) Quantitative cache analysis frameworks (RTAS 2025) Recent Articles span cache timing analysis, speculative execution vulnerabilities, and performance modeling. Keywords include Real-Time Systems , Security , Computer Architecture , and Static Analysis , with sub-fields covering cache persistence, hardware-software contracts, throughput prediction, and formal verification of side-channels. Scientific Awards include an ERC Advanced Grant (2021) , multiple best paper awards (RTAS 2025, DATE 2024, CCS 2023), and the Intel Early Career Faculty Honor Program (2012). Advising and Grants : He actively recruits PhD students and postdocs for hardware-software security research, supported by the ERC grant. His lab's alumni include Dr. Sebastian Hahn, and he has hosted numerous student assistants. Labs and Teams : He leads the Real-Time and Embedded Systems Lab at Saarland Informatics Campus, collaborating on projects like uops.info (Intel microarchitectural profiling) and chi (cache hierarchy inference).

• Computer Arithmetic
• Computer Architecture
• Domain-Specific Accelerators
• +۳ مورد دیگر

David Mallasén Quintana is a Postdoctoral Researcher in Computer Engineering at the Embedded Systems Laboratory (ESL) of École Polytechnique Fédérale de Lausanne (EPFL). He completed his Ph.D. in Computer Engineering at Universidad Complutense de Madrid (UCM) in 2024. His research focuses on computer arithmetic, domain-specific accelerators, and RISC-V core customization, with a strong emphasis on energy-efficient and high-performance computing solutions. Key research contributions include the development of the PERCIVAL open-source RISC-V core integrating Posit and Quire arithmetic, energy-efficient MAC units, and the LiveChess2FEN framework for chessboard digitization using CNNs optimized for the Jetson Nano platform. His work bridges hardware design, algorithm optimization, and embedded systems applications. Publications highlight advancements in Posit arithmetic implementation, low-cost approximate computing units, and RISC-V architecture extensions. Current projects explore scientific computing applications of 64-bit Posit arithmetic and energy-efficient wearables through precision optimization. Lead developer of PERCIVAL RISC-V core Co-developer of LiveChess2FEN framework Contributor to IEEE Transactions on Computers and Emerging Topics in Computing

Josep Altet Sanahujesمشاهده پروفایل

دانشیار

• Integrated Circuit Design
• Thermal Management in Electronics
• RF Circuit Engineering
• +۴ مورد دیگر

Josep Altet Sanahujes is an Associate Professor in the Department of Electronic Engineering at the Polytechnic University of Catalonia (UPC). His research focuses on high-performance integrated circuits, particularly leveraging thermal measurements to characterize and optimize RF analog circuits. He leads the HIPICS (High Performance Integrated Circuits and Systems Design) group, specializing in temperature sensor development for on-chip testing and monitoring of aging effects in CMOS amplifiers. Education: M.S. in Electronic Engineering, La Salle Universitat Ramon Llull (1993) Ph.D., Electronic Engineering Department, Universitat Politècnica de Catalunya (1998) Research Interests: Dr. Altet pioneers thermal-based strategies for analog circuit testing, including the design of compact temperature sensors compatible with RF technologies. He explores thermal coupling characterization and electro-thermal interaction in integrated circuits, with applications in automotive AI, energy-efficient DNN accelerators, and astrophysical instrumentation. His work bridges fundamental physics (e.g., thermal phase lag analysis) with practical device optimization. Key Contributions: His recent articles address cutting-edge topics like energy-efficient mixed-precision DNN inference via binary segmentation, aging compensation in RF amplifiers using DC temperature measurements, and security enhancements through thermal signatures. He has published extensively on topics ranging from heterodyne infrared imaging for current tracking to BPF-based thermal sensors. Lab & Teams: Primary affiliation with the HIPICS research group at UPC, collaborating on interdisciplinary projects involving thermal-aware circuit design and embedded systems.

Diego Mateo Peñaمشاهده پروفایل

دانشیار

• Mixed-Signal Integrated Circuits
• RF Circuit Design
• CMOS Technology
• +۶ مورد دیگر

Diego Mateo Peña is an Associate Professor at the Department of Electronic Engineering at the Universitat Politècnica de Catalunya (UPC), specifically within the Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona. He holds an M.S. and Ph.D. in Electronic Engineering from UPC, completed in 1993 and 1998, respectively. Member of the HIPICS (High-Performance Integrated Circuits and Systems Design Group) and EFRICS (Efficient and Robust Integrated Circuits and Systems) research groups. Expertise includes mixed-signal and RF integrated circuits, substrate noise analysis, UWB-IR circuit design, and thermal monitoring techniques. His research focuses on circuit reliability, aging effects in CMOS devices, and thermal-based characterization. He has co-authored over 50 conference papers and 16 journal articles, with an emphasis on RF circuit design and integrated systems. Key projects involve developing low-power IoT receivers, 22nm FDSOI processors, and thermal-aware circuit monitoring systems. His work bridges theoretical analysis and practical applications in nanoscale electronics and robust system design.

• Cryptography
• Embedded Systems
• Biometrics
• +۵ مورد دیگر

Mariano Lopez Garcia is a researcher at the Polytechnic University of Catalonia (UPC), affiliated with the Department of Electronic Engineering at the Polytechnic School of Engineering of Vilanova i la Geltrú (EPSEVG). He is part of the SARTI research group, focusing on technological development in remote sensing and information processing, as well as the SARTI-MAR subgroup addressing marine environment applications. His work emphasizes embedded systems, cryptography, and biometric security, with a strong emphasis on FPGA-based hardware-software co-design for cybersecurity and post-quantum cryptography solutions. His research spans over 150 activities, including peer-reviewed publications, competitive R&D projects, and conference presentations. Key areas include post-quantum cryptography (e.g., McEliece cryptosystem implementations), biometric authentication systems, FPGA acceleration for real-time processing, and control systems for power electronics. Notable projects include developing secure cryptographic key protection against side-channel attacks and creating low-cost embedded systems for signature verification. He has collaborated on initiatives such as the Projecte R+D+I competititu for vector processors in biometric identification and the TEC2015-68784-R project on scalable identification systems. His contributions also extend to power electronics, including sliding mode control for resonant converters and electronic transformer designs. Recent publications (2025) highlight advancements in post-quantum cryptography using FPGA hardware accelerators and constant-weight code-based encryption. His work bridges theoretical research with practical applications in embedded systems and cybersecurity, often leveraging reconfigurable hardware for efficient and secure solutions.