جستجوی استاد راهنمای دانشگاهی

Daniel Großeمشاهده پروفایل

استاد

• Formal Verification
• Hardware Verification
• Electronic Design Automation
• +۳ مورد دیگر

Prof. Daniel Große serves as Professor at the Institute for Complex Systems (ICS) within Johannes Kepler University Linz, Austria, while maintaining a dual affiliation with the German Research Center for Artificial Intelligence (DFKI) in Bremen. His research centers on Electronic Design Automation (EDA), specializing in verification, debugging, and synthesis of complex hardware/software systems through advanced virtual prototyping techniques. His primary research domains include Formal Verification , Hardware Verification , and Virtual Prototyping , with significant contributions to RISC-V architecture development and embedded systems validation. Current projects like PaSVer (automotive electronics), AUTOASSERT (analog-digital verification), and VerSys (RISC-V software platforms) demonstrate his focus on bridging simulation and formal methods for safety-critical applications. Recent publications reveal accelerating trends in metamorphic testing for embedded graphics libraries and RISC-V vector extensions, alongside innovations in waveform analysis tools like Surfer. His work increasingly integrates AI-assisted verification while maintaining rigorous formal methods foundations. Prof. Große actively supervises student research, having guided Lucas Klemmer's PhD thesis and nine Bachelor theses on topics ranging from RISC-V processor design to transaction visualization. His projects including SATiSFy (autonomous vehicle security) and CONVERS (complex system design automation) secure substantial research funding from academic and industry partners. He leads the Institute for Complex Systems' development of open-source tools such as RISC-V VP++ and contributes to international standards through program committee roles at DATE, ICCAD, and RISC-V Summit Europe.

• Embedded Systems
• Hardware-Software Co-Design
• Invasive Computing
• +۷ مورد دیگر

Prof. Dr.-Ing. Jürgen Teich is a full Professor and Chair for Hardware-Software Co-Design at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU). He serves as Head of Department Computer Science and Vice Dean of the Technical Faculty since August 2024, and has been Speaker of the FAU Research Center Embedded System Initiative (FAU ESI) since 2023. His educational background includes: Diploma degree in Electrical Engineering, University of Kaiserslautern (1989) Dr.-Ing. degree in Electrical Engineering, University of Saarland (1993) Habilitation (PD Dr.-Ing.) entitled "Synthesis and Optimization of Digital Hardware/Software Systems" (1996) Prof. Teich's research focuses on Embedded Systems , Invasive Computing , Hardware-Software Co-Design , and Reconfigurable Computing . His work spans from theoretical foundations to practical implementations, with particular emphasis on resource-constrained systems, many-core architectures, and energy-efficient computing. He has pioneered research in invasive computing paradigms that enable more efficient use of many-core processors by allowing applications to dynamically claim resources. His recent publications reveal a strong trend toward energy-efficient AI deployment on embedded devices , security of embedded systems , and novel memory technologies . There's a clear focus on practical implementations of machine learning on microcontrollers (TinyML), hardware acceleration for data processing, and innovative approaches to power management in self-powered systems. Among his notable scientific awards are: IEEE Fellow (since 2018) Member of Academia Europaea, Section Informatics (since 2011) Member of the National Academy of Science and Engineering (acatech) (since 2018) Member of the German Society of Humboldtians (since 2021) Prof. Teich has been Principal Investigator for numerous DFG-funded projects including SFB/Transregio 89 "Invasive Computing" (2010-2022), SFB 694, and multiple priority programs. He has coordinated large collaborative research efforts across Germany and internationally, with significant funding from DFG and other sources. His research group has produced influential work in embedded systems design and co-design methodologies. He leads the Hardware-Software Co-Design research group at FAU, which focuses on innovative approaches to embedded system design, invasive computing architectures, and efficient implementation of machine learning on resource-constrained devices. The group maintains strong collaborations with industry partners including Intel, Xilinx, and automotive companies.

Daniel Müller-Gritschnederمشاهده پروفایل

استاد مدعو

• TinyML
• Embedded Software Development
• Soft Error Resilience
• +۴ مورد دیگر

Daniel Müller-Gritschneder is an Adjunct Teaching Professor (Privatdozent) at the Technical University of Munich (TUM), affiliated with the Chair of Electronic Design Automation. He leads the 'Electronic System Level' research group, focusing on embedded systems, TinyML, virtual prototyping, and hardware resilience. He temporarily served as head of the Chair of Real-Time Systems (2019–2020) and holds a senior membership in IEEE. His research spans: TinyML : Optimizing neural network inference for microcontrollers. Virtual Prototyping : Fast simulation for embedded software development (e.g., ETISS simulator). Runtime Verification : Hardware monitoring for safety-critical systems. Fault Tolerance : Cross-layer resilience against soft errors. Design Automation : NoC synthesis and RISC-V toolchain optimization. His publications emphasize RISC-V-based systems, TinyML deployment, fault injection, and embedded AI. Recent works show trends toward compiler-assisted security, thermal management, and automated design-space exploration for edge devices. Awards: Best Paper Award (SiPS 2019) Habilitation Award (Bund der Freunde der TUM, 2019) 2nd Best Paper (SMACD'15) Best Paper nominations at DAC'07, DATE'10, Analog'10, NOCS'13 He advises researchers in the Electronic System Level group and contributes to EU projects (e.g., Scale4Edge). His lab develops tools like ETISS, MLonMCU, and Seal5 for RISC-V and TinyML ecosystems.

Marc Reichenbachمشاهده پروفایل

استاد

• Integrated Circuits
• Embedded Systems
• VLSI Design
• +۷ مورد دیگر

Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.

• Embedded Systems
• Compilers
• Hardware-Software Co-Design
• +۵ مورد دیگر

Prof. Dr. rer. nat. Rainer Leupers is a faculty member at RWTH Aachen University, chairing the Department of Software for Systems on Silicon. His research focuses on embedded systems, hardware-software co-design, virtual prototyping, and security in computing-in-memory architectures. He has published extensively on RRAM accelerators, logic locking, and neuromorphic security. Chair of Software for Systems on Silicon Research in hardware security and deep learning accelerators Recent publications on cross-tool virtual frameworks and thermal side-channel attacks His work bridges system-level modeling with practical security implementations, emphasizing reliability and performance in heterogeneous computing environments. Key trends in his 2025-2023 articles include compute-in-memory optimization, neural network inference efficiency, and security vulnerabilities in emerging hardware. Awards and formal recognitions are not explicitly detailed in the provided materials. He has not directly mentioned advising students or research grants in the given text fragments. The chair's contact information includes an office at ICT Cube 1, Electrical Engineering, Aachen, with direct email and website links.

• Electronic Design Automation (EDA)
• Computer Architecture
• Embedded Systems
• +۵ مورد دیگر

Prof. Wolfgang Ecker is a Professor at the Technical University of Munich (TUM), affiliated with the Chair of Design Automation within the TUM School of Computation, Information and Technology . His research focuses on Electronic Design Automation (EDA), RISC-V processor architectures, and hardware-software co-design. He leads projects advancing EDA tools for embedded systems, neural network acceleration, and formal verification methodologies. Ecker's work bridges machine learning techniques with traditional EDA challenges, addressing topics like energy-efficient AI inference and automated documentation generation. His contributions span compiler optimization, FPGA implementations, and fault analysis in digital systems. Recent research highlights include contributions to the TRISTAN project for RISC-V ecosystem development, model-driven architecture frameworks, and AI-driven timing analysis. He actively collaborates on open-source EDA tools and explores Rust-based embedded systems development. Ecker’s lab emphasizes practical applications in edge computing and automotive microcontroller safety, with a strong emphasis on interdisciplinary collaboration across TUM’s CIT School. His publications (15 most recent listed) reflect a focus on EDA tool innovation, processor design, and leveraging machine learning for hardware optimization. While no specific awards are mentioned, his involvement in ERC-funded projects and leadership in international collaborations underscores his academic impact.

• Computer Architecture
• Hardware Design
• Signal Processing
• +۷ مورد دیگر

Prof. Dr.-Ing. Holger Blume serves as Vice President for Research and Transfer at Leibniz University Hannover while maintaining his academic position as Professor in the Architectures and Systems Section within the Faculty of Electrical Engineering and Computer Science. He holds multiple leadership positions including Chairperson of the Research Commission and Central Ethics Committee, Executive Board member of eNIFE (Leibniz Research Initiative for Neurosciences), and membership in both the Laboratory of Nano and Quantum Engineering and L3S Research Centre. His research interests span computer architecture, hardware design, signal processing, AI accelerators, hearing aid technology, and biomedical engineering. His work bridges theoretical computer science with practical applications in automotive systems, medical devices, and quantum engineering. Professor Blume's research demonstrates strong interdisciplinary connections between electrical engineering, computer science, and biomedical applications, with particular emphasis on hardware-oriented solutions for real-world problems. Analysis of his recent publications (2023-2025) reveals a strong focus on hardware acceleration for AI and signal processing applications, particularly in automotive radar/LiDAR systems and hearing aid technology. His work shows consistent innovation in RISC-V processor design, specialized hardware for mathematical functions, and biomedical applications of engineering principles. The research demonstrates a clear trajectory toward energy-efficient, specialized computing architectures for specific application domains. As Vice President for Research and Transfer, Professor Blume oversees significant research initiatives at Leibniz University Hannover, which hosts multiple Clusters of Excellence including PhoenixD (Photonics, Optics, and Engineering), QuantumFrontiers, and Hearing4all. The university participates in numerous collaborative research centers and junior research groups funded by DFG, BMBF, and EU programs. Professor Blume is actively involved in multiple research facilities including the Laboratory of Nano and Quantum Engineering and the L3S Research Centre. His work connects with Leibniz University's research focuses on optical technologies, quantum optics and gravitational physics, and biomedical research and technology. His leadership positions indicate strong involvement in shaping the research strategy and ethical framework of the university's scientific endeavors.

• Computer Architecture
• Parallel Processing
• FPGA Design
• +۳ مورد دیگر

Frank Hannig is a Professor at the University of Erlangen-Nuremberg, Germany, specializing in computer architecture and high-performance computing. His research focuses on FPGA acceleration, hardware-software co-design, neural network optimization, and embedded systems. He has collaborated extensively with co-authors such as Jürgen Teich and Oliver Reiche, producing over 200 publications since 2001. His work emphasizes domain-specific languages (DSLs) for image processing (e.g., Hipacc) and compiler optimizations for FPGAs. Key contributions include techniques for quantized neural networks on microcontrollers, CGRA toolchain evaluation, and efficient mapping of CNNs onto processor arrays. Hannig also explores energy-efficient architectures and reconfigurable computing for emerging applications like edge AI and automotive systems. Publications span conferences like ASAP, FPL, and ARC, reflecting his interdisciplinary approach to bridging algorithm design and hardware implementation. His research often addresses practical challenges in deploying machine learning models on resource-constrained devices while maintaining performance and energy efficiency.

• Electronic Design Automation
• Fault Injection Simulation
• RISC-V Processors
• +۷ مورد دیگر

Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors. University: Technical University of Munich Department: Chair of Design Automation Email: johannes.geier@tum.de Research Interests Electronic Design Automation (EDA) for analog and digital circuits Fault tolerance and reliability in RISC-V architectures Security analysis of post-quantum cryptographic systems Timing analysis and microfabrication techniques Optical Networks-on-Chip (NoC) and emerging technologies Compiler-assisted hardware security implementations Recent Research Trends Specializes in fault injection methodologies for hardware security validation Develops open-source tools like vRTLmod for RTL simulation acceleration Explores RISC-V vector extensions for post-quantum cryptography Investigates differential fault effect equivalence checks for efficiency Designs compiler-based security countermeasures against instruction skip attacks Works on concurrent multi-node XCP proxy server architectures

• Emerging Technologies
• Neuromorphic Hardware
• RISC-V for AI
• +۳ مورد دیگر

Albi Mema is a researcher affiliated with the Chair of AI Processor Design (AI-Pro) at Technische Universität München (TUM). His work focuses on emerging technologies for AI applications, including neuromorphic hardware, reliability engineering, and quantum computing. University: Technische Universität München Department: Chair of AI Processor Design (AI-Pro) Key research areas include: Emerging Technologies for AI Neuromorphic Hardware Reliability in Semiconductor Devices Quantum Computing RISC-V Architecture Machine Learning Computer-Aided Design His recent publications address fault-tolerant hyperdimensional computing, analog computing for AI, FeFET-based neuromorphic systems, and compact majority gate design using FDSOI technology. No scientific awards are mentioned in the provided text.

• Integrated Circuits
• RF Circuit Design
• Low-Power Electronics
• +۳ مورد دیگر

Jean-Baptiste Bégueret is a researcher with extensive contributions to integrated circuits , RF design , and low-power electronics . His work spans analog , digital , and mixed-signal systems.

Marco Guarnieriمشاهده پروفایل

دانشیار

• Security and Privacy
• Program Verification
• Programming Languages
• +۳ مورد دیگر

Marco Guarnieri is an Associate Professor at IMDEA Software Institute in Madrid, Spain. His research focuses on the design, analysis, and implementation of practical systems for securely storing and processing sensitive data, with particular emphasis on security at the hardware-software boundary and microarchitectural attacks and defenses. Guarnieri received his PhD in Computer Science in 2017 from ETH Zurich's Institute of Information Security, following an MSc (2012) and BSc (2010) in Computer Engineering from Università degli Studi di Bergamo. His research spans security and privacy, program verification, programming languages, and formal methods. Guarnieri's work has particularly focused on addressing vulnerabilities related to speculative execution (Spectre attacks), side-channel analysis, hardware-software security interfaces, and leakage contracts. His approach often combines formal verification techniques with practical system implementation to develop robust security solutions. Guarnieri's publications reveal a strong focus on microarchitectural security, with recent work addressing secure speculation countermeasures, compiler security guarantees against Spectre attacks, side-channel security of cryptographic implementations, and hardware-software leakage contracts. His research shows a progression from database security early in his career to the hardware-software security boundary that characterizes his current work. Among his notable achievements are a Best Paper Award at CCS 2024 and Distinguished Paper Awards at CCS 2023 and CCS 2022. His paper 'Hardware-Software Contracts for Secure Speculation' also received a Best Paper Award. Guarnieri actively contributes to the academic community through program committee roles, including the PriSC Steering Committee, and has organized events such as PLMW@PLDI 2023. He is seeking talented researchers (interns, PhD students, and postdocs) to join his group at IMDEA Software Institute to work on security at the hardware-software interface.

Salim Ullahمشاهده پروفایل

پژوهشگر

• Approximate Computing
• FPGA-Based Hardware Accelerators
• Embedded Systems Design
• +۳ مورد دیگر

Salim Ullah is a researcher in the Department of Embedded Systems at Ruhr University Bochum. His work focuses on FPGA-based approximate computing, hardware accelerators, and embedded systems design. He leads the Embedded Systems Team, contributing to advancements in reconfigurable logic and neuromorphic computing. Research Interests: Approximate arithmetic circuits, FPGA design methodologies, neural network implementation on FPGAs Key Projects: AxOCS (approximate operator scaling), AxOMaP (mathematical programming for arithmetic operators), AxOSpike (spiking neural networks for operator design) Publications (2024-2020) highlight innovations in error resilience, quantization techniques, and hardware-software co-design. Collaborations include work on RISC-V emulation (NvMISC), energy-efficient multipliers, and embedded AI acceleration frameworks.

Kun Qinمشاهده پروفایل

پژوهشگر

• Hardware/Software Codesign
• RISC-V Architecture
• Open-Source Hardware
• +۳ مورد دیگر

Kun Qin is a Doctoral Candidate and Research Associate at the Technical University of Munich , affiliated with the IH02 Chair of Computer Architecture and Operating Systems (CAOS) and the I10 Chair of Computer Architecture and Parallel Systems (CAPS). His work focuses on Hardware/Software Codesign , RISC-V Architecture , and Quantum Computing . Current affiliation: Department of Computer Engineering, School of Computation, Information and Technology Research areas: FPGA/ASIC design, quantum-based systems, open-source hardware Teaching: Courses on HDL, Computer Architecture, and Operating Systems (WS23/24–WS24/25) Kun actively participates in academic service as Web Co-Chair for the ACM International Conference on Computing Frontiers (CF'24, CF'25). His research includes FPGA acceleration for RTL verification and quantum control processors. Key scientific achievement: Best Poster Award at SERESSA (2023) . Publications span topics like RISC-V verification frameworks, FPGA-based timing systems, and quantum control processors for superconducting qubits.

• Hardware Trojan Design
• Netlist Reverse Engineering
• Neuro Engineering
• +۲ مورد دیگر

Alexander Hepp serves as a Lecturer at the Chair of Security in Information Technology, Technical University of Munich (TUM), where he contributes to both teaching and cutting-edge hardware security research. His current teaching responsibilities include C++ Lab, Embedded Systems and Security, and Strategic Management for Engineers, where he acts as primary lecturer for the latter course. His research centers on hardware trojan design/identification and netlist reverse engineering within the chair's broader security initiatives. His research portfolio demonstrates deep specialization in hardware security vulnerabilities, with emphasis on hardware trojan insertion/detection methodologies and reverse engineering countermeasures. Recent work explores neuro engineering applications and RISC-V-based security implementations, often leveraging open-source hardware frameworks. His publications reveal consistent innovation in hardware obfuscation techniques and netlist analysis tools, addressing critical gaps in pre-silicon security validation. His 12 publications from 2021-2024 show strong focus on hardware security conferences like DATE and DDECS, with recurring themes in trojan detection, reverse engineering challenges, and cryptographic hardware validation. The research trajectory indicates growing emphasis on practical countermeasures against physical attacks and standardized vulnerability assessment frameworks. Scientific Awards: Best Paper Award at DDECS 2022 for 'Hardware Obfuscation of Digital FIR Filters' No verifiable information exists regarding student advising or grant funding in available sources. He operates within Prof. Sigl's research ecosystem which actively pursues projects in fault attacks, IoT security, physical unclonable functions, and post-quantum cryptography implementations, with recent work emphasizing hardware reverse engineering challenges in advanced semiconductor designs.