Xiaolong Liuمشاهده پروفایل
استادیار
Xiaolong Liu serves as Assistant Professor at Southern University of Science and Technology's School of Microelectronics. His academic journey includes a Ph.D. from Hong Kong University of Science and Technology (2019), M.E. from Tsinghua University (2014), and B.E. from Beijing University of Aeronautics and Astronautics (2010). Prior to his current position, he worked as Staff Engineer at eTopus Technology in Silicon Valley (2019-2021) and completed a postdoc at HKUST. Ph.D. in Electronic and Computer Engineering, Hong Kong University of Science and Technology (2019) M.E. in Microelectronics, Tsinghua University (2014) B.E. in Electronic Engineering, Beijing University of Aeronautics and Astronautics (2010) Dr. Liu's research spans cutting-edge RF/mm-Wave/THz integrated circuit design, focusing on high-performance signal generators , ultra-wideband transceivers , and low-power frequency synthesis . His work addresses critical challenges in 5G/6G communications, terahertz spectroscopy, and high-speed wireline interfaces through innovative CMOS architectures. Technical emphases include varactor-less VCOs, harmonic enhancement techniques, and magnetic tuning mechanisms for millimeter-wave systems. His publication portfolio demonstrates consistent leadership in IEEE flagship journals/conferences (JSSC, TMTT, ISSCC, VLSI), with recent work advancing Class-F oscillators, sub-sampling PLLs, and sub-THz synthesizers. Notable trends include migration toward sub-THz frequencies (2023-2025) , multi-core oscillator architectures , and elimination of harmonic tuning for simplified design. IEEE VLSI Paper Technical Highlights (2019) IEEE CICC Invited Talk (2019) IEEE TVLSI 2023 Best Reviewer Award Top 4 Most Downloaded Paper in TCAS-II (July 2022) Dr. Liu actively mentors students through SUSTech's graduate programs, with advisees consistently earning university-level thesis awards and conference recognitions. His lab maintains strong industry ties through silicon validation and collaborates on cutting-edge tapeouts in 7nm/16nm nodes. Current projects focus on cryo-CMOS interfaces for quantum computing and ultra-wideband transceivers for 6G applications. His research group operates within SUSTech's state-of-the-art microelectronics facility, specializing in mm-Wave/THz characterization and high-speed SerDes validation. The team maintains partnerships with semiconductor foundries for advanced-node prototyping and collaborates with industry leaders on real-world implementation challenges.
