جستجوی استاد راهنمای دانشگاهی

Hayden Kwok Hay SOمشاهده پروفایل

دانشیار

• Reconfigurable Computing
• FPGA-Based Systems
• Computer Architecture
• +۷ مورد دیگر

Prof. Hayden Kwok Hay SO is an Associate Professor at the University of Hong Kong (HKU), affiliated with the Department of Electrical and Electronic Engineering. He currently serves as Acting Director of the School of Innovation and previously co-directed the Computer Engineering Program. His research focuses on reconfigurable computing systems, FPGA-based architectures, and their applications in AIoT, medical imaging, and high-performance computing. He holds a B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley (1998–2007). Prof. So has been recognized with awards such as the IEEE-HKN Teaching Award (2021), Croucher Innovation Award (2013), and multiple teaching excellence awards. He leads the Computer Architecture & System Research Lab (CASR) and co-founded the Joint Lab on Future Cities (JLFC). His work spans FPGA overlay architectures, graph processing systems, and hardware-software co-design for efficient computing. Key research contributions include advancements in FPGA-based reconfigurable systems, sparse dataflow architectures, and medical imaging accelerators. He has secured grants for projects like 'Advanced machine vision guided aquatic surface vehicles' and 'Efficient and Productive Parallel Data Processing in Hybrid FPGA-CPU Clusters.' Prof. So has advised numerous students and researchers, contributing to over 150 peer-reviewed publications. His current projects explore AI hardware acceleration, neuromorphic computing, and FPGA-driven solutions for big data challenges.

Antonio Gonzálezمشاهده پروفایل

استاد

• Computer Architecture
• Microarchitecture
• Compilers
• +۷ مورد دیگر

Antonio González is a full Professor at the Barcelona School of Informatics (FIB), Universitat Politècnica de Catalunya (UPC), where he is affiliated with the Department of Computer Architecture. He leads the Microarchitecture and Compilers (ARCO) research group, focusing on robust and energy-efficient computing systems, including general-purpose processors, GPUs, and cognitive computing architectures. His research spans computer architecture, microarchitecture, compilers, GPU design, and deep learning acceleration, with a strong emphasis on energy efficiency and memory optimization. His work integrates hardware and compiler techniques to enhance performance in modern computing systems. The recent publications highlight a strong trend in energy-efficient DNN acceleration, GPU microarchitecture, memory systems, and near-data processing. His team explores novel quantization methods, adaptive caching, and architectural extensions for vision and AI workloads, published in top-tier venues such as MICRO, ISCA, and IEEE/ACM journals. ACM Fellow (2020) ICREA Academia Award (2014, 2019, 2024) UPC Duran Farell Award (2008) HiPEAC 2024 Paper Award (twice) González has supervised several PhD students and leads competitive R&D+i projects, including those funded by ICREA and the European Research Council. His research group collaborates extensively within UPC and with international institutions. He is actively involved in advancing computer architecture through innovation in simulation, hardware design, and AI acceleration. He is a member of IEEE and ACM, and his work continues to influence both academic and industrial developments in high-performance and energy-efficient computing.

Tosiron Adegbijaمشاهده پروفایل

دانشیار

• Computer Architecture
• Embedded Systems Design
• Low-Power Embedded Systems
• +۱۴ مورد دیگر

Tosiron Adegbija is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Arizona, where he serves as Director of Graduate Studies and Thomas R. Brown Endowed Fellow. He is a member of the Graduate Faculty and actively contributes to research and teaching in computer architecture and embedded systems. Education: PhD in Electrical and Computer Engineering, University of Florida, 2015 MS in Electrical and Computer Engineering, University of Florida, 2011 BS in Electrical Engineering, University of Ilorin, Nigeria, 2005 His research centers on energy-efficient computing with a focus on bio-inspired computer architecture , including spiking neural network (SNN) accelerators and in-memory computing. He also explores domain-specific architectures , adaptable memory systems , and microprocessor optimizations for IoT . His work leverages novel memory technologies like STT-RAM to enhance performance and reduce energy consumption in embedded and resource-constrained systems. Recent publications highlight trends in hybrid SNN acceleration, domain-specific accelerator generation, and system-level design space exploration. His research is increasingly focused on neuromorphic computing, automated hardware design, and ultra-efficient architectures using emerging materials like antiferromagnetic tunnel junctions. Scientific Awards: National Science Foundation (NSF) CAREER Award (2019) Elected IEEE Senior Member (2020) Best Paper Award at IEEE ISVLSI (2014) Teaching Award, University of Arizona (2018) ACM GLSVLSI Travel Award (2015) He advises numerous graduate and undergraduate students, many of whom have pursued careers at institutions like Pacific Northwest National Labs, Micron Technology, and Amazon. He has secured significant funding, including a $1.9M NSF FuSE2 grant for energy-efficient computing. His lab collaborates with UA Physics, CMU, and UNL. He has also developed educational tools for Chipyard and RISC-V, supporting hands-on learning in computer architecture. Labs and Research Teams: Leads a research group focused on bio-inspired and domain-specific computing, fostering innovation in energy-efficient hardware. The lab emphasizes hardware/software co-design, neuromorphic engineering, and real-world deployment in IoT and biomedical applications.

Jing Liمشاهده پروفایل

دانشیار

• Computer Architecture
• Compiler Design
• Distributed Systems
• +۷ مورد دیگر

Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.

• Computer Architecture
• Interconnection Networks
• Approximate Computing
• +۵ مورد دیگر

Natalie Enright Jerger is a Professor in the Department of Electrical and Computer Engineering at the University of Toronto's Faculty of Applied Science and Engineering. She holds the Canada Research Chair in Computer Architecture and serves as Director of the Division of Engineering Science (2023-2028). Previously, she was the Percy Edward Hart Professor (2016-2019). She received her B.S. in Computer Engineering from Purdue University (2002), and M.S./Ph.D. in Electrical Engineering from University of Wisconsin-Madison (2004/2008). Her research focuses on: Multi/many-core architectures and on-chip networks Cache coherence protocols and memory hierarchy optimization Approximate computing and sustainable systems Intermittent computing for energy-harvesting devices Hardware acceleration for machine learning Her publications demonstrate strong emphasis on networks-on-chip (NoC) innovations, including routing algorithms, deadlock handling, power-efficient designs, and topology optimizations. Recent work expands into approximate computing, mobile architectures, and ML-driven hardware design. Major Awards: Fellow of Engineering Institute of Canada (2023) McLean Senior Fellow (2019) IEEE Micro Top Picks (2016) ACM/IEEE Microarchitecture Hall of Fame (2015) Sloan Research Fellowship (2015) Canada Research Chair (current) Distinguished Scientist, ACM Fellow, IEEE She leads the NEJ research group and collaborates with industry partners including Intel, AMD, Qualcomm, and IBM. Her work is funded by NSERC, CFI, and industrial grants. She co-chaired ASPLOS 2023 and HPCA 2014, and actively promotes diversity through WICARCH and ACM initiatives.

• Embedded Systems
• Cyber-Physical Systems
• Computer Architecture
• +۵ مورد دیگر

Aviral Shrivastava is a Professor at the School of Computing and Augmented Intelligence, Arizona State University, leading the Make Programming Simple Lab. He holds a Ph.D. and M.S. from the University of California-Irvine (2006, 2002) and a Bachelor’s from IIT Delhi (1999). His research focuses on making programming simple for embedded and cyber-physical systems, with a particular interest in manycore and accelerated computing, software for CPS, and resilient/fault-tolerant computing. He has co-authored over 120 publications in top venues like DAC, ESWEEK, and ACM TECS, with more than 3000 citations and 5 granted patents. His work has been recognized with multiple awards, including the 2010 NSF CAREER award and best paper nominations. Research Areas: Embedded and Cyber-Physical Systems Compiler Design for Modern Architectures Resilient and Fault-Tolerant Computing Scientific Awards: 2010 NSF CAREER award DAC 2017 Best Paper Award Candidate VLSI 2016 Best Student Paper Award LCTES 2010 Second Highest Ranked Paper ASPDAC 2008 Best Paper Candidate Advising & Grants: He has mentored 9 Ph.D. and over 20 Masters students. His research has been funded by NSF, DOE, NIST, SFAZ, and industry partners, totaling $3.5M. He teaches courses on computer organization, architecture, and embedded systems, with student evaluations averaging over 4/5. He also serves as General Chair of Embedded Systems Week (ESWEEK) and holds editorial roles in IEEE ESL, ACM TCPS, and ACM TECS.

Tom Conteمشاهده پروفایل

استاد

• Computer Architecture
• Compiler Optimization
• Manycore Architectures
• +۴ مورد دیگر

Tom Conte is an academic leader with a joint appointment in the School of Electrical & Computer Engineering and School of Computer Science at Georgia Institute of Technology. As the founding director of the Center for Research into Novel Computing Hierarchies (CRNCH), he specializes in computer architecture and compiler optimization. His work focuses on manycore architectures, energy-efficient microprocessor design, and embedded system architectures. Prior to Georgia Tech, he directed the Center for Embedded Systems Research at North Carolina State University. He holds IEEE Fellow status and served as 2015 President of the IEEE Computer Society, co-leading the IEEE Rebooting Computing Initiative since 2011. Dr. Conte earned his bachelor’s degree in Electrical Engineering from the University of Delaware (1986), followed by M.S. and Ph.D. degrees in Electrical Engineering from the University of Illinois at Urbana-Champaign (1988 and 1992). His research has been recognized with prestigious awards including the IEEE Computer Society’s Golden Core Member award and the National Science Foundation’s CAREER Award (1996). His research interests span quantum computing, 3D chip architectures, energy-efficient processing, and post-Moore computing innovations. He has pioneered initiatives like the Superstrider architecture and CREEPY energy-efficient processing frameworks. Recent work includes advancements in quantum programming languages (e.g., Qwerty) and hybrid quantum-classical systems. Awards: IEEE Fellow, Young Alumni Achievement Award, CAREER Award Leadership: IEEE Computer Society President (2015), CRNCH Director Key Projects: Rebooting Computing Initiative, Superstrider Architecture His lab’s contributions include novel compiler optimizations for manycore systems, smart NIC offloading techniques, and thermodynamically inspired computing models. Conte’s work bridges academic research with industry needs through interdisciplinary collaborations and standardization efforts.

Trevor E. Carlsonمشاهده پروفایل

استادیار

• Computer Architecture
• Hardware/Software Co-Design
• Performance Modeling
• +۴ مورد دیگر

Trevor E. Carlson is an Assistant Professor at the School of Computing, National University of Singapore (NUS), focusing on high-efficiency microarchitectures, hardware/software co-design, and secure chip design for IoT and server applications. He earned his Ph.D. in Computer Science from Ghent University (2014) and B.Sc./M.Sc. in Electrical & Computer Engineering from Carnegie Mellon University (2002/2003). Research Interests include energy-efficient processors, secure computing platforms, neuromorphic accelerators, and fast simulation methodologies. He co-developed the Sniper Multi-Core Simulator used globally for performance/power evaluation. Scientific Awards : Best Paper Award, International Conference on Embedded Computer Systems (2016) Best Paper Award, International Symposium on Performance Analysis of Systems and Software (2013) Heidelberg Laureate Forum participation (2015) HiPEAC Technology Transfer Award for Sniper Simulator (2013) Current Research involves secure Systems-on-Chip (SOCure project), hardware security for IoT, and simulation methodologies. He leads a lab with researchers working on topics like Capstone for trustless secure memory access and LABS for laser fault injection benchmarks.

• Superconducting Logic
• Bio-based Architectures
• Novel Computing Mediums
• +۶ مورد دیگر

Dr. Jennifer Volk is an Assistant Professor at the College of Engineering, University of Wisconsin-Madison, specializing in Electrical & Computer Engineering. Her research focuses on leveraging novel technologies like superconductor electronics and photonics to create efficient systems for datacenters, neuromorphic computing, quantum computing, and space/sensing applications. She employs a holistic approach spanning circuit design, materials science, and computer microarchitecture. PhD (2024), University of California, Santa Barbara BS (2016), University of California, Santa Cruz Her research interests include superconducting logic , bio-based architectures , and novel computing mediums , emphasizing co-optimization of logic and circuit blocks. Her work develops design abstractions to simplify adoption of unconventional technologies. Dr. Volk's publications demonstrate expertise in superconducting circuit design, radiation-hardened CMOS for particle physics, and photonic materials. She has received numerous awards including the 2025 John D. Wiley Assistant Professorship and IEEE fellowships in applied superconductivity. 2025 John D. Wiley Assistant Professorship 2024 UC Santa Barbara President's Dissertation Year Fellowship 2023 IEEE CSC Graduate Study Fellowship in Applied Superconductivity 2022 IEEE Micro Top Picks Honorable Mention 2021 IEEE Micro Top Picks She teaches E C E 340 - Electronic Circuits I (Spring 2025). Her work bridges materials science, circuit design, and system architecture to enable next-generation computing platforms.

Mateo Valero Cortésمشاهده پروفایل

استاد

• Computer Architecture
• High-Performance Computing
• Parallel Computing
• +۳ مورد دیگر

Mateo Valero Cortés is a renowned Professor of Computer Architecture at the Polytechnic University of Catalonia and Director of the Barcelona Supercomputing Center (BSC). He has held academic and leadership roles since 1974, advancing high-performance computing (HPC) and computer architecture research. His work includes pioneering contributions to vector architectures, multithreading, and instruction-level parallelism. Education includes a Telecommunications Engineering degree from the Polytechnic University of Madrid (1974) and a PhD in Telecommunications Engineering from the Polytechnic University of Catalonia (1980). His research spans over 700 publications, focusing on HPC systems, parallel computing, and supercomputing infrastructure. Key research interests include vector processing, super-scalar processors, and task-based programming models. Recent work emphasizes scalable architectures for exascale computing and energy-efficient hardware-software co-design. Notable achievements include the Eckert-Mauchly Prize (highest in computer architecture), Seymour Cray Award, and Charles Babbage Prize. He has led initiatives like the Spanish Supercomputing Network (RES) and PRACE (European HPC partnership). Academic affiliations include the Royal Academy of Engineering of Spain, ACM Fellow, and IEEE Fellow. He has received 13 honorary doctorates and awards such as Mexico’s Order of the Aztec Eagle. Current projects include the Mont-Blanc HPC prototype and ERC-funded research on multi-core chip design. His BSC oversees over 300 researchers and manages MareNostrum supercomputers.

Labros Bisdounisمشاهده پروفایل

استاد

• CMOS Circuit Design
• Low-Power Electronics
• Embedded Systems
• +۴ مورد دیگر

Labros Bisdounis is a Professor at the Department of Electrical and Computer Engineering, University of the Peloponnese, Greece. He previously held positions at the Technological Educational Institute of Western Greece, including Associate Professor, Full Professor, and Dean of the School of Technological Applications (2016–2018). He has extensive industry experience as a senior research engineer and project manager at Intracom S.A. (2000–2008), focusing on VLSI circuits and telecom applications. His research interests include CMOS circuit timing/power modeling, low-power/high-speed design, MOSFET modeling, and sensor applications. He has authored over 30 papers with 740+ citations and is an IEEE member. Education: Diploma in Electrical Engineering (1992), University of Patras Ph.D. in Electrical Engineering (1999), University of Patras Research Interests: CMOS circuit timing and power dissipation modeling Deep-submicron/nano-CMOS circuit design MOSFET device modeling Low-power embedded systems and SoC Sensor applications and organic electronics Leadership Roles: Dean of the School of Engineering, University of the Peloponnese (2023–present) Director of Training & Lifelong Learning Centre (2019–2019) Board Member, Hellenic NARIC (2016–2019) Collaborations: Active at the Hellenic Open University as a tutor in Computer Architecture and Digital Systems modules. Co-developed the AETHER framework for pervasive computing and contributed to energy-aware SoC designs for 5 GHz WLANs.

Greg Stittمشاهده پروفایل

استاد

• Computer Engineering
• Embedded Systems
• Reconfigurable Computing
• +۵ مورد دیگر

Greg Stitt is a Professor in the Department of Electrical and Computer Engineering at the University of Florida, affiliated with the College of Engineering. His research focuses on reconfigurable computing, FPGA acceleration, embedded systems, and compiler design. He has received notable awards including the NSF CAREER Award (2012-2017) and the Undergraduate Teacher of the Year Award (2014). His work emphasizes elastic computing frameworks, intermediate fabrics for FPGA virtualization, and warp processors for dynamic hardware/software partitioning. Education: PhD, Computer Science, University of California-Riverside, 2007 BS, Computer Science, University of California-Riverside, 2000 Research Interests: Reconfigurable computing, FPGAs, GPUs, and their applications in high-performance computing Compiler optimization and synthesis techniques for embedded systems Elastic computing frameworks for heterogeneous systems Approximate computing and energy-efficient architectures Grants & Awards: National Science Foundation (NSF) grants for elastic computing (CNS-0914474) and intermediate fabrics (CNS-1149285) Recognition for contributions to FPGA-based scientific computing tools Teaching: Current courses include Reconfigurable Computing 2 and Digital Design Past course offerings span embedded systems, compiler design, and hardware architecture Labs & Teams: Active research in FPGA acceleration, novel architectures, and security for reconfigurable systems Contributions to the Novo-G scalable reconfigurable supercomputing project

Fan Yaoمشاهده پروفایل

دانشیار

• Computer Architecture
• Hardware Security
• AI Security
• +۵ مورد دیگر

Fan Yao is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Central Florida's College of Engineering and Computer Science. She received her Ph.D. in Computer Engineering from The George Washington University in 2018 and currently leads the Computer Architecture and Systems Research (CASR) lab. Her research focuses on the intersection of computer architecture, security, and machine learning, with particular emphasis on hardware-based security vulnerabilities and defenses. Dr. Yao's research interests span computer architecture, hardware and system security, AI security, energy-efficient computing, and cloud computing. Her work addresses critical security challenges in modern computing systems, particularly focusing on microarchitecture attacks, hardware-based model tampering in deep learning systems, and information leakage threats in emerging non-volatile memory systems. She has developed innovative defense mechanisms against cache timing channels, branch predictor vulnerabilities, and GPU-based side channels. Her recent publications demonstrate a strong focus on AI security (particularly Deep Neural Network vulnerabilities), hardware security (including cache and branch predictor attacks), and secure memory architectures. The research shows an evolution from traditional computer architecture topics toward the security implications of AI hardware and emerging memory technologies, with increasing emphasis on practical attacks and defenses in real-world systems. NSF GW I-Corps Site Grant Award, 2018 Best Dissertation Award, GWU, 2018 The Norris & Betty Hekimian Engineering Endowment Fellowship, GWU, 2017 Top Picks in Hardware and Embedded Security, 2019 NSF CAREER project award, 2024 Dr. Yao currently leads multiple NSF-funded research projects including 'Understanding and Taming Deterministic Model Bit Flip Attacks in Deep Neural Networks' (NSF SaTC, 2020-2023), 'Towards Secure-By-Design Integration of Emerging Non-Volatile Memory in Future System' (NSF CNS, 2020-2023), and 'Architecting Secure-by-Design Memristor-Based Memories' (NSF CNS, 2019-2022). She has successfully mentored numerous PhD students, many of whom appear as first authors on top-tier conference publications, demonstrating her commitment to graduate education and research mentorship. As the leader of the CASR lab, Dr. Yao oversees a vibrant research group focused on building secure-by-design, efficient, and advanced future systems through novel techniques spanning hardware, computer architecture, and systems. The lab actively publishes at top computer architecture and security conferences including ISCA, MICRO, HPCA, IEEE S&P, and USENIX Security, with multiple papers accepted to these venues annually. The group has developed several influential tools and frameworks for security analysis, including proof-of-concept code for BranchSpec exploits that has been widely cited in the hardware security community.

• Computer Architecture
• Microarchitecture
• Compilers
• +۷ مورد دیگر

Antonio Maria Gonzalez Colas is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture within the Faculty of Computer Science of Barcelona (FIB). He leads the ARCO research group focused on Microarchitecture and Compilers and is actively engaged in high-impact research in computer architecture, GPUs, and energy-efficient computing. His collaborations extend to the Barcelona Supercomputing Center and various national and European research initiatives. Research Interests: His primary research areas include computer architecture, microarchitecture, compilers, GPUs, and processor design. He focuses on energy-efficient computing, deep neural network (DNN) accelerators, GPU simulation and optimization, memory systems, and architectural support for machine learning and autonomous systems. His work often integrates compiler techniques with hardware design for performance and efficiency. Scientific Production Trends: His recent publications demonstrate a strong focus on energy-efficient hardware for AI workloads, particularly DNN and speech recognition acceleration, GPU architectural innovations, memory optimization, and real-time rendering. He frequently publishes in top-tier venues such as ISCA, MICRO, HPCA, and IEEE/ACM journals. ICREA Academia Award 2024 HiPEAC 2024 Paper Award ACM Senior Member (2020) Advising and Grants: He has advised numerous PhD students whose theses cover topics like energy-efficient architectures for autonomous driving, speech recognition, and neural networks. He leads competitive R&D projects, including an ERC Advanced Grant and projects funded by the Spanish National Program and the ICREA Academia program, focusing on domain-specific architectures and cognitive computing units. Labs and Teams: He is the principal investigator of the ARCO (Microarchitecture and Compilers) research group at UPC, a leading team in computer architecture research in Spain. The group is part of a larger collaborative network within UPC and with international partners.

Per Stenströmمشاهده پروفایل

استاد

• Computer Architecture
• Memory Systems Optimization
• Energy-Efficient Computing
• +۳ مورد دیگر

Professor Per Stenström is affiliated with the Department of Computer Science and Engineering at Chalmers University of Technology . His research focuses on computer architecture , memory systems optimization , and energy-efficient computing , with significant contributions to DNN accelerator design and cache management . Research Trends : His recent publications emphasize Memory compression techniques for energy efficiency Hardware-software co-design for DNN acceleration Security in microarchitectural optimizations Hybrid memory systems for near-memory computing These works span both theoretical and applied aspects of computer architecture, with a particular focus on data redundancy elimination , parallel processing , and quality-of-service constraints . His work has influenced the development of energy-aware resource management frameworks and resilient EU HPC systems , as evidenced by his long-standing contributions to the field since the early 2010s.