Takeshi Ikenaga is a Professor at Waseda University’s School of Fundamental Science and Engineering and Graduate School of Information, Production and Systems . He earned his Ph.D. in Information & Computer Science from Waseda University in 2001, following B.E. and M.E. degrees in Electrical Engineering (1988–1990). His career spans roles at NTT LSI Laboratories (1990–2002), Kitakyushu Foundation for Advancement of Industry, Science and Technology (FAIS) (1999–2002), and visiting researcher at the University of Massachusetts (1999–2000). Research Interests : Application-specific SoCs for video/image processing, including compression (H.264/AVC, H.265/HEVC), filters (super-resolution, noise reduction), recognition systems (feature detection, object tracking), and communication (UWB, LDPC). He also works on many-core processor design, ultra-low-delay vision systems, and sports analytics (volleyball, figure skating) with real-time 3D pose estimation and ball tracking. Awards : Recipient of the Furukawa Sansui Award (Waseda University, 1988) IEICE Research Encouragement Award (1992) Multiple Best Paper/Presentation Awards (2006–2022) at conferences including DAC/ISSCC, LSI IP Design, ISOCC, ISPACS, and CVIT APSIPA Distinguished Lecturer Certificate (2015) Waseda University Presidential Teaching Award (2020)
Professor David Thomas holds the position of Professor in Computer Engineering at the University of Southampton's Electronics and Computer Science Department. His research focuses on the intersection of software and hardware, particularly leveraging FPGAs for novel digital architectures and event-driven computing. He has a notable academic trajectory, having previously served as a Lecturer and Senior Lecturer at Imperial College London before joining Southampton in 2021. Dr. Thomas is actively involved in supervising PhD students and contributes to interdisciplinary research projects funded by the EPSRC, such as the SONNETS initiative exploring scalable event-triggered systems. Education: BSc in Computer Science (Imperial College London), PhD in Digital Architectures (Imperial College London). Postdoctoral roles included Research Associate and Research Fellow at Imperial's Department of Computing. Research Interests: Event-driven computing, FPGA-based systems, high-level synthesis, and high-performance computing. His work emphasizes practical implementations of theoretical models, such as custom processors and application-specific accelerators. Current projects include optimizing random number generation for FPGAs and exploring meta-programming techniques for hardware design. Advising and Grants: Supervises multiple PhD students in areas like neuromorphic computing and algorithm optimization. Active in securing funding for distributed system architectures and FPGA-based solutions. Labs/Teams: Member of the Cyber Physical Systems research group. Collaborates with interdisciplinary teams on projects like POETS (Partially Ordered Event-Triggered Systems) for large-scale parallel computing.
Prof. Dr. Estela Suarez is a Professor of High Performance Computing at the Institute for Computer Science, University of Bonn (W2 in the Jülich Model) and Joint Lead of the Division "Novel System Architecture Design" at the Jülich Supercomputing Centre (JSC), Forschungszentrum Jülich GmbH. She also leads the Research Group "Next Generation Architectures and Prototypes" at JSC and serves as Spokesperson of Helmholtz Information Program 1, Topic 2. Currently on sabbatical during the 2024/2025 and 2025 academic years, she remains active in research leadership roles. 2010: PhD in Physics from University of Geneva, Switzerland 2004: Master in Physics, Specialization in Astrophysics, University Complutense of Madrid, Spain Professor Suarez specializes in high performance computing with particular expertise in heterogeneous HPC system architectures and modular supercomputing architecture (MSA). Her research spans hardware prototyping and evaluation, system software development, operational data analysis, and co-design methodologies. She has pioneered approaches to address hardware heterogeneity through system-wide orchestration of diverse computing resources, enabling more efficient scientific computing across multiple domains. Her work bridges theoretical computer architecture with practical implementation challenges in exascale computing environments, focusing on real-world applications that require specialized hardware configurations. Professor Suarez's publication record shows a clear evolution from foundational work on the DEEP project (2016) through the development of modular supercomputing concepts (2019-2021) to current applications across diverse scientific domains (2022-2024). Her recent publications demonstrate how modular architectures can be effectively applied to climate modeling, neuroscience simulations, quantum chemistry calculations, and other computationally intensive fields. This trend highlights her focus on practical implementation challenges and the growing importance of adaptable computing architectures in modern scientific research. 2023/2024 Lehrpreis der Universität Bonn: UniBonn teaching award Professor Suarez has secured significant research funding through major projects including NUMERIQS (Projects A05, B02, and Z02), European Processor Initiative (EPI), DEEP-SEA (Software for Exascale Architectures), IFCES2 (optimization of simulation algorithms for exascale supercomputers), and AIDAS (virtual laboratory between Forschungszentrum Jülich and CEA on AI and data analytics). While currently not accepting new students due to sabbatical, she has previously mentored graduate students in high performance computing techniques and has delivered numerous invited lectures at international conferences. Professor Suarez leads the "Next Generation Architectures and Prototypes" research group at JSC and serves as Joint Lead of the "Novel System Architecture Design" division. She chairs the Research and Innovation Advisory Group (RIAG) from EuroHPC Joint Undertaking since 2024. Her work involves close collaboration with international research teams on advancing supercomputing architectures, including contributions to the University of Bonn's new HPC system "Marvin" which ranks on both the TOP500 and GREEN500 lists.
Dr Graeme Bragg is a Senior Teaching Fellow at the University of Southampton within the Department of Electronics and Computer Science . His work spans teaching, research, and technical development with a focus on event-driven computing, bioinformatics, and computational modeling. He actively supervises PhD students and collaborates on interdisciplinary projects. Research Interests: Parallel computing, event-driven systems, genotype imputation, Petri net simulations, subglacial hydrology modeling Teaching: Specializes in hardware description languages and computational methods for engineering students Technical Expertise: RISC-V architecture, FPGA acceleration, bespoke compute fabric development His recent publications demonstrate expertise in applying event-driven computing to diverse problems including: 2025: Automated marking systems for SystemVerilog labs 2025: Seasonal dynamics in subglacial hydrology 2023: Genotype imputation using custom hardware 2022: Optimization algorithms and graph analysis Current research explores: Custom RISC-V FPGA clusters for bioinformatics Event-triggered systems for scientific simulations Parallel computing solutions for molecular modeling Contact: gmb@ecs.soton.ac.uk | +44 23 8059 2784
Roberto Giorgi is an Associate Professor of Computer Engineering at the Department of Information Engineering, University of Siena, Italy. He has held this position since October 1, 2006, following his tenure as an Assistant Professor since March 15, 1999. His educational background includes a Ph.D. in Computer Engineering from the University of Pisa (1999) with a thesis on coherence protocols for shared-memory multiprocessors, and an Electronic Engineering degree (1995) with a thesis on trace-driven performance evaluation of multiprocessors. Giorgi's primary research focuses on Computer Architecture , particularly on multiprocessor/multicore issues including processor design, coherence protocols, programmability, and energy efficiency. His work spans both theoretical and practical aspects of computer architecture, with emphasis on real-world implementations and educational tools. He has coordinated significant EU-funded projects including AXIOM (2014-2018) on Smart Cyber-Physical Systems and TERAFLUX (2009-2014) on Many-Cores. His recent publications (2022-2025) demonstrate a strong progression toward practical applications of computer architecture research, with particular emphasis on RISC-V architecture, FPGA-based acceleration, dataflow computing models (especially DF-Threads), and graph processing. Many of his papers address educational tools for computer architecture education, real-time object detection on embedded platforms, and novel execution paradigms for edge computing and HPC. IEEE Senior Member ACM Lifetime Member Coordinator of EU-funded AXIOM project (2014-2018) on Smart Cyber-Physical Systems Coordinator of EU-funded TERAFLUX project (2009-2014) on Many-Cores Giorgi has been actively involved in securing research funding and building collaborations, particularly in high-performance computer architecture research with emphasis on scalable architectures and embedded systems. He leads the Computer Architecture Lab (ROOM 223) at the University of Siena, which was established in 2007, and has been instrumental in developing practical implementations of architectural concepts including the AXIOM platform for cyber-physical systems.
Khalil Esper is a Researcher at the Department of Computer Science, Faculty of Engineering, Friedrich-Alexander-University Erlangen-Nuremberg (FAU), where he works at the Chair of Computer Science 12 (Hardware-Software Co-Design). His research focuses on verification, energy optimization, and runtime requirement enforcement in embedded systems and MPSoCs. His educational background includes: Informatics Engineering from Aleppo University, Syria (2010-2015) European Master in Embedded Computing Systems (EMECS) from Rhineland-Palatinate University of Technology Kaiserslautern-Landau (Germany) and Norwegian University of Science and Technology (Norway) (2017-2019) Esper's research interests center around verification and model checking, energy optimization on MPSoC, real-time systems and embedded systems, and autonomic computing. His work particularly focuses on runtime requirement enforcement mechanisms for non-functional properties in multi-processor systems-on-chip, with applications extending to medical devices and human-robot interaction systems. He has developed approaches using finite state machines, reinforcement learning, and evolutionary algorithms to ensure system properties are maintained during execution. His publication record shows a strong trend toward applying formal methods and runtime enforcement techniques to increasingly complex systems, with recent work expanding into safety-critical applications like orthoses and human-robot interaction. The interdisciplinary nature of his research bridges computer science, embedded systems engineering, and biomedical applications. Esper has supervised multiple theses including: Sascha H.: Runtime Requirement Enforcement of Non-Functional Requirements on MPSoCs Using Fuzzy Logic (2022) Iana S.: Feedback-Based Control of Non-functional Program Execution Properties on Linux (2023) Philipp L.: Runtime Requirement Enforcement of Functional and Non-Functional Requirements of a Knee Orthosis Based on a Digital Twin (2024) Avinash N.: Runtime Requirement Enforcement of Safety Properties of an Ankle Orthosis Based on a Digital Twin (2024) Zhiyi T.: Generation of Environment FSMs Using Machine Learning Techniques (2025) Moustafa A.: Runtime Requirement Enforcement of Safety Properties of Human-Robot Interaction Based on a Digital Twin (2025) Florian K.: Runtime Requirement Enforcement of Safety Properties of Human-Robot Interaction (2025) He has been actively teaching courses on Approximate Computing and Embedded Systems since the 2021/2022 academic year, demonstrating his commitment to academic instruction alongside his research activities. Esper is involved in the InvasIC research project, part of the DFG Transregional Collaborative Research Center 89 on Invasive Computing, which explores novel approaches to resource management in parallel computing systems.
Dr Tomasz Kazmierski is an Associate Professor in the Department of Electronics and Electrical Engineering at the University of Southampton. His research focuses on hardware security, VLSI design, and energy-efficient computing. He leads projects such as the EPSRC-funded 'Next Generation Energy-Harvesting Electronics' and 'Event-based parallel computing (POETS)'. Current Projects: Event-based parallel computing (EPSRC) Next Generation Energy-Harvesting Electronics (EPSRC) Supervision: PhD students Peiyao Sun, Xuan Ji, and Haosen Yu Research Interests: Hardware Security & Trojan Resilience Approximate Computing Ultra-Low Power Circuits Neural Network Accelerators Recent work emphasizes secure design of neural network hardware, optimization of VLSI interconnects, and aging-aware circuit techniques. His publications span conferences like IEEE ISCAS and IEEE AsianHOST, addressing topics from fault-tolerant signal processing to energy-harvesting systems.
David Black-Schaffer is a Professor at Uppsala University's Department of Information Technology, specializing in computer systems research. As of 2023, he serves as Dean of Research for the Faculty of Science and Technology. His work bridges software and hardware innovations to enhance data movement efficiency in computer systems, with applications commercialized through a startup and integrated into industry standards like OpenCL. Black-Schaffer earned his PhD in Electrical Engineering from Stanford University in 2008, focusing on many-core processor programming. His career spans roles at Apple Inc. (contributing to OpenCL standards), postdoctoral research at Uppsala University, and academic progression from assistant to full professor (2010–2017). He has held leadership roles including Head of the Division of Computer Systems (2022) and department representative on the faculty Advisory Committee for Research (2021). His research spans computer architecture, memory systems, parallel programming, and simulation techniques. Recent publications (2024–2020) explore garbage collection, cache optimization, memory contention, NUMA systems, and instruction scheduling. Key trends include software-hardware co-design for power efficiency, reuse-aware data placement, and machine learning for performance modeling. Knut & Alice Wallenberg Foundation: Wallenberg Academy Fellowship Prolongation (2020–2025), Wallenberg Academy Fellow (2016–2021) Swedish Research Council (VR): Project Grant (2019–2024), Young Researcher Grant (2015–2018), Framework Grant (2012–2017) European Research Council: ERC Starting Grant (2017–2022) Teaching Awards: Uppsala Engineering and Science Student Union Pedagogical Prize (2012), Uppsala University Pedagogical Prize (2016), Uppsala Technical Physics Students' Teaching Award (2019) Other Grants: ScalableLearning flipped classroom project (2012–2020), Arm Ltd. collaborations on memory system designs He pioneered flipped-classroom teaching through the ScalableLearning project, impacting over 80,000 students. His research is conducted in collaboration with institutions like Arm Ltd., with past contributions to Apple's OpenCL implementation and UPMARC research center.
Michael Hines is a Senior Research Scientist in the Department of Neuroscience at the Yale School of Medicine. His work focuses on developing and optimizing computational tools for neural modeling, notably the NEURON simulation environment. This software enables researchers to model cellular and network mechanisms involved in neurological disorders and therapeutic interventions. Hines holds a PhD from the University of Chicago (1975) and has contributed extensively to computational neuroscience through software development and interdisciplinary collaboration. Education: PhD, University of Chicago, 1975 MS, Physics, University of Chicago, 1972 BS, Physics, Michigan State University, 1970 His research interests revolve around advancing computational methods for simulating neural systems, including the development of dynamic clamp techniques and real-time interfacing with living cells. He has collaborated with institutions globally to enhance the scalability and accuracy of NEURON for supercomputing environments. Hines' work bridges neuroscience, mathematics, and computer science, addressing challenges in modeling complex neural networks and their applications to disease mechanisms. Publications highlight his contributions to neural simulation software, error analysis in computational models, and interdisciplinary tools like ModelDB and SenseLab. His research underscores the integration of experimental and computational approaches to advance understanding of neurological disorders and therapeutic strategies. Labs/Teams: Hines leads the development of the NEURON Simulation Environment and contributes to collaborative projects in computational neuroscience at Yale.
Gianluca Tempesti is Reader in Intelligent Systems at the University of York, researching bio-inspired hardware and fault-tolerant computing. His work applies biological principles to develop resilient computing architectures using FPGAs and many-core systems. Research innovations: Self-repairing embryonic machine architectures Evolutionary mapping of image filters Artificial bee colony task management POEtic reconfigurable tissue platform He directs postgraduate research in electronic engineering and intelligent systems.
Prof. A.D. Pimentel holds a full professorship at the Informatics Institute of the University of Amsterdam, leading the Parallel Computing Systems (PCS) group within the Systems and Networking Lab. His research focuses on multi-core and multi-processor systems, emphasizing performance, energy efficiency, dependability, and productivity in system design and runtime management. He earned his PhD and MSc in Computer Science from the University of Amsterdam in 1998 and 1993, respectively. Current roles: Chair of PCS group, Board member of Advanced School for Computing and Imaging (ASCI), and ICT Research Platform Nederland (IPN) Teaching: Courses on Multi-core Processor Systems, Embedded Software, and Architecture Research interests span edge AI, sustainable computing, and system-level modeling. Recent work includes innovations in energy-efficient scheduling, thermal management in 3D-stacked systems, and adaptive CNN inference at the edge. Over 25 years of contributions to embedded systems design space exploration and hardware/software co-design have been recognized through awards like the IEEE CEDA Outstanding Service Award (2025). Awards: IEEE DATE Fellow (2025), NWO Knowledge & Innovation Covenant grant lead Active in conference organization, serving as General Chair for Embedded Systems Week (2026) and Design Automation and Test in Europe (DATE 2024). Engages in cross-disciplinary projects like improved secure semiconductor evaluation (ISSE) and energy labeling for digital services.
Li-Shiuan Peh is a Provost's Chair Professor in the Department of Computer Science at the School of Computing, National University of Singapore (NUS) . She previously held faculty positions at MIT (2013-2016) and Princeton University (2002-2009), advancing from Assistant to full Professor. Education: B.S. from National University of Singapore (1995) Ph.D. from Stanford University (2001) Her research focuses on energy-efficient hardware systems , spanning neural network accelerators for edge computing , privacy-preserving embedded systems , on-chip communication networks , and hardware security . Current projects include AI-on-skin interfaces , secure Network-on-Chip (NoC) architectures , and low-power wearable sensors . Scientific Awards: IEEE Fellow (2017) National Research Foundation Returning Singaporean Scientist Award (2016) ACM Distinguished Scientist (2011) MICRO Hall of Fame Award (2011) National Science Foundation CAREER Award (2003) Her work has driven innovations in bufferless NoC architectures , collaborative traffic advisory systems , and laser attack benchmarks , with publications in top venues like DATE, NOCS, and DAC. She leads an interdisciplinary research group at NUS, advising graduate students in computer architecture and hardware security.
Jürgen Teich is a Professor at the University of Erlangen-Nuremberg, Department of Computer Science. His research focuses on computer architecture, embedded systems, and hardware-software co-design, with particular emphasis on energy-efficient and sustainable computing. He leads projects involving FPGA-based accelerators, neural networks on microcontrollers, and real-time systems optimization. His work spans topics such as approximation computing, MPSoCs (Multiprocessor Systems-on-Chip), and IoT device architectures. Key contributions include methodologies for optimizing resource allocation in heterogeneous systems and developing energy-harvesting solutions for embedded systems. Teich has authored numerous publications in top-tier conferences and journals, including DATE, FPL, and ACM Transactions. His research often collaborates with industry partners, emphasizing practical applications and open-source hardware.
Aaron Stillmaker is an Associate Professor and Chair of the Electrical and Computer Engineering Department in the Lyles College of Engineering at California State University, Fresno. Previously, he served as the director of the LCOE Honors Program from 2022-2025 and was an Assistant Professor at California State University, Fullerton in Fall 2016. His academic career builds upon extensive research experience at the VLSI Computation Lab at UC Davis where he earned his PhD. Dr. Stillmaker's educational background includes: Ph.D. in Electrical and Computer Engineering from University of California, Davis (2015) M.S. in Electrical and Computer Engineering from University of California, Davis (2013) B.S. in Computer Engineering (Magna Cum Laude) from California State University, Fresno (2008) His research focuses on the design and implementation of energy-efficient many-core processor arrays, with particular expertise in VLSI design, physical many-core architectures, and parallel processing algorithms. His work addresses fundamental challenges in scaling processor architectures beyond traditional multi-core designs, with emphasis on communication efficiency, power management, and application-specific optimizations. Dr. Stillmaker has made significant contributions to the development of the KiloCore processor array containing 1000 independent processing cores. Analysis of his publication record shows a consistent trajectory from fundamental research on CMOS scaling and processor architecture to practical implementations of many-core systems. His work demonstrates strong interdisciplinary connections between computer architecture, VLSI design, and application-specific computing, with increasing focus on energy efficiency metrics and practical implementation challenges as technology nodes shrink. Dr. Stillmaker has served as a reviewer for prestigious journals including IEEE Transactions on VLSI Systems, IEEE Journal of Solid-State Circuits, and IEEE Micro. He has also been active in professional service as a Chapter Advisor for CA-L Tau Beta Pi Chapter at UC Davis. His teaching responsibilities at Fresno State include courses such as ENGR 1H/3H: Engineering Honors Seminar, ECE 106: Switching Theory and Logical Design, and ECE 243: VLSI Physical Design. He maintains regular student success hours both in-person and via Zoom to support student learning. Professional experience includes internships at Intel Labs (Circuit Research Lab) in Hillsboro, OR and at Pelco Inc., providing him with valuable industry perspective that informs his academic work and teaching.
Estela Suarez is a Professor of High Performance Computing at the University of Bonn's Computer Science Department and holds leadership roles at the Jülich Supercomputing Centre (JSC) in Forschungszentrum Jülich. Her work focuses on advancing modular supercomputing architectures, heterogeneous systems, and application optimization for exascale computing. She currently serves as Chair of the EuroHPC Joint Undertaking's Research and Innovation Advisory Group (RIAG) and leads the Next Generation Architectures and Prototypes research group at JSC. Education includes a PhD in Physics from the University of Geneva (2010) and a Master's in Physics (Astrophysics specialization) from Universidad Complutense de Madrid (2004). She has held senior research positions at JSC since 2010 and has led major EU-funded projects like DEEP, DEEP-ER, and DEEP-SEA. Research interests include HPC system design, hardware-software co-design, and energy-efficient supercomputing architectures. She was awarded the University of Bonn's 2023/2024 teaching award and actively contributes to initiatives like the European Processor Initiative (EPI) and the NUMERIQS consortium. Current projects include optimizing exascale systems for Earth system modeling (IFCES2), AI-driven data analytics (AIDAS), and modular supercomputing software (DEEP-SEA). During her 2024/2025 sabbatical, she is not accepting new students. Her work is published in journals like Geoscientific Model Development and conferences such as ISC and EuroHPC.
