جست‌وجوی استاد و پژوهشگر

Yuan Yaoمشاهده پروفایل

استادیار

• Computer Architecture
• Parallel Computing
• Power and Thermal Management
• +۷ مورد دیگر

Yuan Yao serves as an Assistant Professor in the Department of Information Technology at Uppsala University, Sweden. His academic role spans teaching and research within the Computer Systems division, focusing on cutting-edge computer architecture and parallel computing systems. He maintains active collaborations across international institutions, particularly in energy-efficient hardware design and emerging computing paradigms. His educational journey includes: B.S. in Micro-electronics from Northwestern Polytechnical University, China (2009) M.S. in System-on-Chip Design from KTH Royal Institute of Technology, Sweden (2014) Ph.D. in Electrical Engineering and Computer Science from KTH Royal Institute of Technology (2019) Yao's research centers on power and thermal management for chip multi-processors, Network-on-Chips (NoCs), and GPUs. He pioneers hardware/software co-design for high-performance computing, coherency mechanisms for emerging memory technologies, and performance analysis of on-chip networks. Recent work expands into neural network acceleration and battery-less Internet of Things architectures, reflecting a trajectory toward energy-constrained specialized systems. His methodology integrates formal modeling with practical implementation for real-world impact. Publication trends reveal consistent innovation in energy efficiency across parallel architectures. From foundational DVFS techniques for NoCs (2016-2018) to recent breakthroughs in battery-less IoT (2023-2024), his work demonstrates evolutionary progression toward novel computing domains. Key thematic threads include thermal-aware optimization, memory consistency protocols, and hardware acceleration for AI workloads, with applications spanning data centers to embedded systems. Scientific recognition includes: Best paper candidate at IEEE International Symposium on High Performance Computer Architecture (HPCA) 2018 for in-network packet generation research Yao actively supervises graduate researchers and leads collaborative projects in computer architecture. His grant portfolio supports work on battery-less IoT systems and neural network accelerators, though specific funding details aren't publicly enumerated. Current projects emphasize sustainable computing through novel architectures for energy-harvesting environments. He operates within Uppsala University's Computer Systems division, contributing to research groups focused on hardware acceleration, embedded systems, and networked architectures. His lab environment fosters interdisciplinary work bridging computer architecture, energy harvesting, and machine learning for next-generation computing platforms.

• Integrated Circuits
• RF Circuit Design
• Low-Power Electronics
• +۳ مورد دیگر

Jean-Baptiste Bégueret is a researcher with extensive contributions to integrated circuits , RF design , and low-power electronics . His work spans analog , digital , and mixed-signal systems.

Michael Swiftمشاهده پروفایل

استاد

• Operating Systems
• Computer Architecture
• Device Drivers
• +۴ مورد دیگر

Michael Swift is Professor of Computer Sciences at the University of Wisconsin-Madison within the College of Letters and Sciences. He leads the Sonar research group and co-leads the Multifacet architecture group with Mark Hill, while contributing to the Wisconsin Institute on Software-defined Datacenters (WISDoM). His research centers on operating system/hardware interaction, with seminal work in device driver reliability (Nooks, Shadow Drivers), memory systems (storage-class memory integration), and cloud security. Projects like Microdrivers and Carburizer address driver complexity and fault tolerance, while recent work explores learned OS policies and heterogeneous processor support. Analysis of his 2023-2025 publications reveals intensifying focus on memory tiering, security in cloud environments, and hardware-accelerated systems, with growing integration of machine learning for system optimization. Key awards include: Best paper award at OSDI 2004 Best paper award at SOSP 2003 Best paper award at the 3rd Asia-Pacific Workshop on Networking (2019) Professor Swift mentors numerous PhD students (current and past) and secures research funding through NSF grants CNS-0915363 and CNS-0745517 plus Google support. He serves as Instructional Program Director and chairs both the Space committee and Diversity, Equity, and Inclusion committee. The Sonar group drives innovation in system support for emerging hardware technologies, while Multifacet focuses on computer architecture advancements, particularly in heterogeneous computing and memory systems.

• Computer Architecture
• Distributed Systems
• Cloud Computing
• +۳ مورد دیگر

Javier Picorel is a former researcher at École Polytechnique Fédérale de Lausanne (EPFL), affiliated with the Parallel Systems Architecture Lab (Parsa). His work focuses on computer architecture, distributed systems, and cloud computing, with an emphasis on optimizing storage systems, near-data processing, and high-performance computing. Picorel has contributed to advancements in scalable serverless computing, secure data center architectures, and accelerator design. His research interests include storage-class memory hierarchies, virtual machine performance optimization, and software-defined systems. Key projects include BlockNDP for block-storage acceleration, IndiLog for stateful serverless systems, and SPARTA for accelerator address translation. He has collaborated extensively with the Parsa group and published widely in top conferences such as ISCA, MICRO, and PACT.

Onur Mutluمشاهده پروفایل

استاد

• Computer architecture
• Bioinformatics
• Computer memory systems
• +۷ مورد دیگر

Onur Mutlu is a Full Professor of Computer Science at ETH Zurich (since 2015), with adjunct professor positions at Carnegie Mellon University (since 2016) and Bilkent University (since 2015). His academic career spans prestigious institutions including Carnegie Mellon University where he served as Assistant Professor (2009-2013) and Strecker Early Career Endowed Professor (2013-2016). His research focuses on computer architecture, particularly memory systems, with expertise in: Computer memory systems and DRAM architecture Multi-core processor design Fault tolerance and reliability Hardware/software interactions Systems security related to hardware Emerging memory technologies Dr. Mutlu's work has significantly impacted both academic research and industry practices. His discovery of the RowHammer problem created a new field at the intersection of hardware reliability and systems security. His research on memory controllers, flash memory reliability, and emerging memory technologies has been adopted by major technology companies including Samsung, Intel, IBM, and Microsoft. His numerous scientific awards include the IEEE Computer Society Harry H. Goode Memorial Award (2025), IFIP Jean-Claude Laprie Award (2024), Huawei OlympusMons Award (2023), IEEE Computer Society Edward J. McCluskey Technical Achievement Award (2020), and ACM SIGARCH Maurice Wilkes Award (2019). He is an IEEE Fellow (2018), ACM Fellow (2017), and member of Academia Europaea (2018). Dr. Mutlu has received significant industry recognition with Faculty Awards from Google, Facebook, HP, Huawei, IBM, Intel, Microsoft, NSF, and VMware. His work has earned over 20 Best Paper awards and 12 papers selected for IEEE Micro's Top Picks as some of the most influential papers in computer architecture. He maintains strong industry connections, having worked at Microsoft Research (2006-2009), Intel (multiple summers), AMD (multiple summers), VMware (2016), and Google (2016), enabling direct technology transfer of his research ideas into commercial products.

• Computer Architecture
• Parallel Processing
• Memory Systems
• +۷ مورد دیگر

Llaberia Griño, Jose M. is a faculty member in the Department of Computer Architecture at the Faculty of Computer Science of Barcelona (FIB), Universitat Politècnica de Catalunya (UPC). He has been actively involved in research and academic activities for several decades, contributing significantly to the field of computer architecture. His research interests lie primarily in computer architecture, with a focus on high-performance computing, memory systems, cache management, interconnection networks, and parallel processing. He has made notable contributions to the design and optimization of cache hierarchies, particularly in multicore and non-volatile memory systems, and has explored innovative techniques such as reuse detection, data compression, and systolic array implementations. The trends in his recent publications indicate a sustained focus on improving the performance, efficiency, and reliability of memory systems, especially last-level caches using emerging non-volatile technologies like STT-RAM. His work often combines architectural innovation with practical modeling and forecasting techniques to evaluate system behavior. Among his scientific recognitions is participation in The 2nd Cache Replacement Championship (CRC-2) , highlighting his expertise in cache algorithms. Llaberia has advised doctoral students such as Ana Bosque Arbiol and Rubén Gran Tejero. He has been a key participant in numerous competitive R&D projects, including 'Computación de Altas Prestaciones' and 'HIPEAC 3 - European Network of Excellence', demonstrating sustained funding and collaborative research efforts. He is a member of the CAP - Grup de Computació d'Altes Prestacions (High-Performance Computing Group) at UPC, a leading research group in computer architecture and high-performance systems.

• Microelectronics
• Emerging Memories
• Neuromorphic Computing
• +۵ مورد دیگر

Hassen AZIZA is a senior Associate Professor and Head of the Memory Team (MEM) within the IM2NP research unit at Aix-Marseille University, specializing in microelectronics and emerging memory technologies. His work bridges academic research and industrial applications through collaborations with ST-Microelectronics, CEA-Leti, Thales, and international universities. He earned both his Master of Science in Electrical Engineering (MSEE) and PhD with honors from Aix-Marseille University. His educational background established the foundation for his expertise in semiconductor devices and memory systems. His research centers on Microelectronics , Emerging Memories , and Neuromorphic Computing , with specific focus on RRAM reliability, computation-in-memory architectures, and hardware security. Current projects address critical challenges in RRAM variability, fault tolerance, and energy-efficient neural network implementations using memristive crossbars. His work spans from fundamental device physics to system-level integration for IoT and biomedical applications. Analysis of his 15 most recent publications reveals dominant trends in RRAM reliability engineering (35% of articles), neuromorphic hardware implementation (30%), and sensor system development (20%). Key subfields include fault-tolerant memory design, variability-aware neural networks, and low-power IoT circuit optimization, demonstrating consistent focus on bridging device physics with practical system requirements. Best Paper Award at IEEE ETS (2021) for RRAM fault analysis CoolGames Silver Medal (2019) for high-altitude balloon project Eiffel Scholarship for PhD student (2018) Guillemin-Cauer Best Paper Award (2014) Multiple IEEE conference best paper awards (2013, 2011) SIMagine contest finalist/silver medalist (2010, 2009) He has supervised 10 PhD students (8 graduated via industry-oriented CIFRE theses), including Eiffel scholarship recipient Hussein BAZZI. His research is funded through strategic industry partnerships with ST-Microelectronics, CEA-Leti, and Thales Silicon Security, plus European initiatives like the French Tech LAB grant for the SMILE air quality monitoring startup project. Current grants focus on RRAM commercialization and neuromorphic hardware development. As leader of the Memory Team (MEM) within IM2NP's Department of Analysis and Design of Electronic Systems, he directs research on resistive memories, neuromorphic circuits, and sensor interfaces. The team maintains strong industry links through joint projects with semiconductor manufacturers and participates in international standardization efforts for emerging memory technologies.

Vijay Narayananمشاهده پروفایل

استاد

• Power Aware Computing
• Computer Architecture
• Embedded Systems
• +۴ مورد دیگر

Vijay Narayanan is the Robert Noll Chair Professor in Computer Science & Engineering and Electrical Engineering at Pennsylvania State University. He co-directs the Microsystems Design Lab and leads research in embedded visual analytics, self-powered processors, and system design using emerging devices. Education: B.E in Computer Science and Engineering (1993) from University of Madras, India Ph.D. in Computer Science and Engineering (1998) from University of South Florida, USA His research spans Power Aware Computing , Computer Architecture , and Embedded Systems , with emphasis on Visual Cortex on Silicon and Self-Powered Processors . Current work includes Non-Volatile Processors and Design Automation under unreliable power conditions via NSF ERC ASSIST. Recent publications focus on GPU architecture (Tensor Cores, ACE), Memory Consistency Verification (QED), and Neural Radiance Fields (Disorf, Distwar) for robotics and rendering. Key collaborations include Tsinghua University and DARPA/SRC LEAST Center . Scientific Awards: IEEE Fellow ACM Fellow He leads the Architecture, Benchmarking and Circuits Thrust in the DARPA/SRC LEAST Center and contributes to NSF ERC ASSIST for self-powered systems. Grants and projects emphasize cross-layer optimizations and hardware-software co-design.

Andreas Andreouمشاهده پروفایل

استاد

• Neuromorphic Engineering
• CMOS Microsystems
• Sensory Information Processing
• +۶ مورد دیگر

Andreas Andreou is a Professor of Electrical and Computer Engineering at Johns Hopkins University (JHU), with secondary appointments in Computer Science and the Whitaker Biomedical Engineering Institute. He co-founded the JHU Center for Language and Speech Processing (CLSP) and co-directs the Andreou Lab, focusing on brain-inspired microsystems, neuromorphic engineering, and biomedical sensors. His research spans CMOS-based neuromorphic processors, event-based vision systems, and wearable health monitoring devices like the StethoVest. Key contributions include silicon retinas, polarization-sensitive imagers, and algorithms for pattern analysis. Research Interests: Neuromorphic Computing: Designing energy-efficient brain-inspired chips using 3D CMOS, FETs, and memristive technologies. Biomedical Microsystems: Wearable acoustic sensors for cardiac monitoring and vestibular prosthetics. AI Hardware: Neuromorphic accelerators for edge computing, leveraging LLMs for automated circuit design. Notable Achievements: IEEE Fellow (since 2020) Recipient of the 3rd Best Paper Award at IEEE BioCAS 2018 $2M DARPA grant for bio-inspired event cameras Labs/Teams: The Andreou Lab collaborates with the Kavli Neuroscience Discovery Institute and NSF-funded neuromorphic projects. Ongoing work includes neuromorphic Ising machines, LLM-driven chip design, and quantum sensing for medical applications.

• Low-Power Integrated Circuits
• High-Speed CMOS Design
• Reconfigurable Circuits
• +۶ مورد دیگر

Marco Lanuzza is an Associate Professor in the scientific disciplinary sector ING-INF/01-Electronics at the Department of Computer Engineering, Modeling, Electronics, and Systems (DIMES) at the University of Calabria. He obtained his degree and Ph.D. in Electronic Engineering from the "Mediterranea" University of Reggio Calabria in 2000 and 2005, respectively, and has taught at the University of Calabria and other institutions since 2005-06. He holds the National Scientific Qualification for Full Professor in Electronics (2019) and is a Senior Member of IEEE (2016). Education: Electronic Engineering (110/110), Ph.D. in Electronic Engineering Research Focus: Low-power/high-speed CMOS circuits, reconfigurable circuits, nanotechnology optimization Editorial Roles: Associate Editor for Elsevier's 'Integration, the VLSI Journal' and Wiley's 'International Journal of Circuit Theory and Applications' His research spans circuit design, nanotechnology validation, and applications in signal processing and IoT. Recent publications highlight innovations in content-addressable memory, PUF architectures, and STT-MRAM for in-memory computing. Key subfields include energy-efficient memory systems, hardware security, and cryogenic electronics. Scientific Awards: Senior Member of IEEE (2016) National Scientific Qualification for Full Professor (09/E3 - Electronics, 2019) Associate Editor for two major journals Marco Lanuzza contributes extensively to international conferences as Program Chair and TPC Member. He is part of the Nanoelettronica e Microsistemi research group at DIMES, focusing on multidisciplinary electronic systems and sensor design.

Joachim Falkمشاهده پروفایل

پژوهشگر

• Electronic System Level Design
• Hardware-Software Co-Design
• Data-Flow Graphs
• +۶ مورد دیگر

Joachim Falk is a researcher at the Department of Hardware-Software Co-Design (Computer Science 12) at Friedrich Alexander University Erlangen-Nuremberg. With over 20 years of experience since joining the department in 2004, he specializes in electronic system level design, dataflow programming, and hardware-software co-design, contributing significantly to the field through publications, teaching, and research leadership. His educational background includes: Doctorate degree (Dr.-Ing.) in Computer Science from FAU (2014) Diploma degree in electrical engineering (data processing) from Georg-Simon-Ohm University of Applied Science Nuremberg (2002) Falk's research focuses on Electronic System Level Design, Hardware/Software Code Generation for Data-Flow Graphs, Compiler Optimizations, and Parallel Architectures. His work bridges theoretical computer science with practical embedded systems implementation, particularly through the SystemC framework and his contributions to the SysteMoC language. He actively explores energy-efficient computing approaches for dataflow networks and embedded systems, with recent work emphasizing self-powering networks, clock and power gating techniques, and multi-reader buffer implementations for heterogeneous architectures. His recent publication trends reveal a consistent focus on optimizing dataflow networks for energy efficiency and performance. Key themes include self-powering dataflow networks, innovative clock and power management techniques, buffer management strategies for heterogeneous many-core systems, and invasive computing approaches. His research demonstrates a strong connection between theoretical models and practical implementation challenges in embedded systems design. Dr. Falk teaches courses including 'Entwicklung interaktiver eingebetteter Systeme' (Development of Interactive Embedded Systems) for Winter Semester 2024/2025 and 'SystemC' for Summer Semester 2024, supervising multiple theses on security modeling at the electronic system level and sleep/wake-up strategies for hardware implementations of dataflow networks. His research is conducted within the framework of projects like SysteMoC (representation of computational models in SystemC) and SystemCoDesigner (design space exploration for embedded systems).

• Computer-Aided Design
• Energy-Efficient Systems
• VLSI Design
• +۳ مورد دیگر

Sarma Vrudhula is a Professor at the School of Computing and Augmented Intelligence, Arizona State University (ASU). He holds a Ph.D. in Electrical Engineering from the University of Southern California (1985). Previously, he was a professor at the University of Arizona and served as the founding director of the NSF UA/ASU Center for Low Power Electronics. He is an IEEE Fellow recognized for contributions to low-power and energy-efficient digital circuit design. Educations: Ph.D. Electrical Engineering, University of Southern California (1985) M.S. Electrical Engineering, University of Southern California (1980) Bachelor's in Mathematics (Computer Science and Mathematical Statistics), University of Waterloo, Canada (1976) Research Interests: His work focuses on design automation, energy management in digital systems, statistical analysis of process variations, threshold logic circuits, and emerging technologies. He has pioneered methodologies for low-power VLSI design, thermal management of multi-core processors, and hardware implementations of threshold logic using spintronic devices. Publications: His recent research includes scalable energy-efficient architectures for AI, in-memory computing, and reconfigurable threshold logic gates. Key topics span energy efficiency in edge computing, neuromorphic systems, and sustainable VLSI design. Awards: IEEE Fellow (2005) Best Paper Award (2008) for macro cell characterization methodology Service & Grants: He led the NSF IUCRC Consortium for Embedded Systems and served on editorial boards. His grants include projects on threshold logic synthesis, energy-aware embedded systems, and hardware acceleration for neural networks. Courses Taught: Algorithmic Foundations of CAD for Digital Systems Computer Architecture Discrete Mathematics for Engineers

• Computer Architecture
• Systems & Networking
• Approximate Computing
• +۶ مورد دیگر

Weng Fai WONG is an Associate Professor and Deputy Head of the Department of Computer Science at the School of Computing, National University of Singapore (NUS). With over three decades of academic experience at NUS, he has established himself as a leading researcher in computer systems, with particular expertise in the interface between hardware and software stacks. Dr. Wong received his B.Sc. (First Class Honors) and M.Sc. from the National University of Singapore in 1989 and 1991 respectively, followed by a Dr.Eng.Sc. from the University of Tsukuba in 1993. His academic journey began at NUS (then DISCS) in 1985, where he progressed from student to Senior Tutor in 1989, and later returned from Japan as a Lecturer in 1993. Dr. Wong's research focuses on systems and networking, with special emphasis on hardware-software co-optimization. His current research interests include approximate computing , neuromorphic computing , and hardware acceleration for deep learning. His work spans computer architecture , embedded systems , compilers and runtime systems , and programming languages . He has made significant contributions to optimizing software for novel hardware including FPGAs, GPUs, and non-volatile memory technologies. His recent publications (2023-2025) demonstrate a strong focus on energy-efficient AI computing, with particular emphasis on spiking neural networks, large language model acceleration, and FPGA-based solutions for graph processing and machine learning workloads. His research shows a clear trajectory toward green AI through hardware-software co-design that minimizes energy consumption while maintaining computational effectiveness. Dr. Wong is a Member of ACM and a Senior Member of IEEE. His paper "Exploiting half precision arithmetic in Nvidia GPUs" was a Best Paper Finalist at the IEEE High Performance Extreme Computing Conference (HPEC 2017). As Deputy Head of the Department of Computer Science at NUS, Dr. Wong plays a key leadership role in academic administration while maintaining an active research program. His work has been supported by numerous research grants, though specific details are not provided in the available information. Dr. Wong leads research in the Systems & Networking area at NUS, with particular focus on the Hardware-Software Interface Laboratory. His team explores innovative approaches to bridge the gap between theoretical computer science and practical hardware implementation, with applications spanning from edge computing to large-scale data centers.

Park Ki-hoمشاهده پروفایل

دانشیار

• Computer Architecture
• Embedded System Design
• IoT System Design
• +۴ مورد دیگر

Dr. Park Ki-ho is an Associate Professor at the Department of Computer Engineering, Sejong University. His research focuses on computer architecture, embedded systems, IoT systems, and low-power design methodologies. Academic Background: PhD in Computer Science from Yonsei University Professional Experience: Senior Engineer at Samsung Electronics, Post-Doctoral Research Associate at University of Utah Research Interests: Develops innovative solutions for sensor hub design , memory systems , and machine learning hardware acceleration . Key areas include: Non-Volatile Memory (NVM) management 3D Integrated Circuit memory bandwidth optimization Intelligent Edge Device architectures Hybrid Cache Architectures Model Compression Techniques On-Device AI Processing Recent Publications demonstrate expertise in in-memory acceleration , sparse matrix representation , and large language model inference . His work bridges theoretical advancements with practical implementations for IoT and AI applications.

Mark Hempsteadمشاهده پروفایل

استاد

• computer architecture
• computer systems
• power-aware computing
• +۷ مورد دیگر

Mark Hempstead is a Professor in the Department of Electrical and Computer Engineering and Computer Science at Tufts University's School of Engineering. He leads the Tufts Computer Architecture Lab (TCAL) and has made significant contributions to computer architecture, systems research, and interdisciplinary applications of engineering tools to human subject research. Dr. Hempstead received his BS in Computer Engineering from Tufts University (Summa Cum Laude), and his MS and Ph.D. in Engineering from Harvard University, where he worked with Professors David Brooks and Gu-Yeon Wei. Prior to joining Tufts University in 2015, he was an Assistant Professor at Drexel University. His research focuses on increasing energy efficiency across circuits, architecture, and systems boundaries. Current research areas include: Computer architecture and systems Power-aware computing and embedded systems Mobile computing and machine learning systems Workload characterization and quantum computing Learning sciences and computer systems for human subjects research His group has published in several research communities including high-performance computer architecture, workload characterization, design automation, mobile systems, embedded systems, quantum computing, and Internet-of-Things. Recent publications show a strong trend toward machine learning systems, quantum computing architecture, and thermal management in modern processors, with applications spanning from embedded systems to high-performance computing platforms. Dr. Hempstead has received numerous scientific awards and honors: NSF CAREER award (2014) Allen Rothwarf Award for Teaching Excellence from Drexel University (2014) Excellence in Research Award from Drexel College of Engineering (2014) Winner of industry-sponsored SRC student design contest (2006) Best Paper Nominee in HPCA 2012 He has secured significant research funding including NSF Engineering Resource Center for Engineering Tools for Innovation and Research in Education (EnTIRE), multiple NSF grants including a CAREER award, DARPA funding, and industry collaborations with Google, Honeywell, and Facebook. His current research grants focus on hardware/software error detection, STEM education understanding, next-generation memory systems, and PCB assurance using thermal side-channel analysis. Dr. Hempstead leads the Tufts Computer Architecture Lab (TCAL), which investigates methods to increase energy efficiency across circuits, architecture, and systems. The lab has explored applications ranging from embedded systems and IoT to chip multiprocessors and high-performance computing. Current projects include systems support for machine learning, non-volatile memory design, thermal hotspot management, security implications of thermal side channels, automatic hardware accelerator generation, privacy-aware databases, and quantum computer architecture for ion-trap systems.