Yanan Guo is an Assistant Professor in the Department of Computer Science at the University of Rochester, specializing in computer architecture and cybersecurity. Her research focuses on GPU memory safety, side-channel attacks, quantum computing, and machine learning security, with recent projects exploring cross-VM side-channel vulnerabilities and quantum circuit simulation. PhD, University of Pittsburgh (advisor: Dr. Jun Yang) Her work bridges hardware and software security, addressing issues like GPU cache eviction mechanisms, memory corruption attacks, and adversarial threats in neural networks. She actively collaborates with researchers like Youtao Zhang and Jun Yang, with publications in top venues including USENIX Security, MICRO, and ICML. Recent publications highlight trends in GPU security (memory safety, side-channel attacks), quantum computing optimizations, and adversarial machine learning. Her team’s projects have received recognition such as the NSF OAC grant for AI workflow security and features in IEEE Transactions on Computers. Featured Paper in IEEE Transactions on Computers (02/22 issue) Shortlisted for Top Picks in Hardware and Embedded Security 2023 Dr. Guo mentors PhD students and offers weekly office hours for undergraduates, emphasizing career paths, graduate applications, and research guidance. She serves on program committees for conferences like USENIX Security and ASPLOS.
Timothy M. Jones is a Professor of Computer Architecture and Compilation at the University of Cambridge's Computer Laboratory, serving as Director of the Computer Architecture and Semiconductor Design Centre (CASCADE) and Fellow/Director of Studies at Gonville and Caius College. His research focuses on parallelism extraction in applications to enhance performance and address energy efficiency/reliability challenges in compilers, binary translators, and microarchitectures. Current work includes novel cache prefetching techniques, thread-level parallelism schemes, and advanced core prediction methods. He has an Erdős number of 4 and a Dijkstra number of 4 via collaborative networks. Research interests span computer architecture fundamentals, compiler optimizations, hardware security mechanisms, and fault tolerance strategies. Notable contributions include speculative vectorization, heterogeneous parallel error detection (MEEK/FireGuard), and security tools like MarkUs and MineSweeper. CASCADE oversees interdisciplinary projects addressing future microprocessor/system challenges. Jones supervises PhD students through CASCADE's 2025 intake program. Publications emphasize architectural innovations in memory systems, security, and energy efficiency. Key works include MASCOT (memory dependence prediction), Scalar Vector Runahead (2024), and Decoupled Vector Runahead (2023). His work integrates hardware-software co-design principles to tackle real-world processor bottlenecks.
Baris Kasikci is an Associate Professor in the Paul G. Allen School of Computer Science & Engineering at the University of Washington. Previously (2017-2023), he was a Morris Wellman Assistant Professor in the Electrical Engineering and Computer Science Department at the University of Michigan. His research focuses on building efficient and trustworthy computer systems through innovative combinations of approaches from systems, computer architecture, and programming languages. Dr. Kasikci received his PhD in Computer Science at EPFL and has held research positions at Microsoft Research Cambridge, Google, Intel, and VMware. His work addresses critical challenges in system reliability, security, and performance in increasingly complex software ecosystems. His research interests center on improving the efficiency of datacenter applications and machine learning systems, analyzing and fixing failures, and enhancing hardware security. His lab develops techniques for automated bug detection, formal verification of distributed systems, and building systems support for heterogeneous hardware architectures. Recent projects include Whisper (profile-guided branch misprediction elimination), Huron (taming false sharing), and Agamotto (automatic detection and repair of bugs in persistent memory applications). Analysis of his recent publications shows a strong trend toward optimizing large language model serving, hardware security, and performance optimization for modern heterogeneous architectures. His work bridges traditional systems research with emerging AI infrastructure needs, particularly in efficient LLM serving, security vulnerabilities in modern hardware, and performance optimization for heterogeneous computing environments. NSF CAREER award Microsoft Research Faculty Fellowship Intel Rising Star Award VMware Early Career Faculty Grant Google Faculty Award Roger Needham PhD Award (best PhD thesis in computer systems in Europe) Patrick Denantes Memorial Prize (best PhD thesis at EPFL) Best Paper Award at OSDI'18 Best Paper Award at MICRO'22 Dr. Kasikci has advised numerous PhD students who have gone on to prestigious positions in academia and industry, including Tanvir Ahmed Khan (Assistant Professor at Columbia University), Akshitha Sriraman (Assistant Professor at CMU), and Jiacheng Ma (AMD). His research has been supported by significant grants from NSF, DARPA, Intel, Google, Microsoft, VMware, and Amazon. His lab, the EfesLab, focuses on building tools and techniques that make computer systems more reliable, secure, and efficient. The EfesLab, led by Dr. Kasikci, brings together postdocs, PhD students, and undergraduate researchers to tackle fundamental challenges in systems reliability and performance. The lab has developed numerous influential tools including Whisper, Huron, and Agamotto that address critical performance and reliability issues in modern computing systems. Current research directions include efficient LLM serving, security of emerging hardware technologies, and automated debugging techniques.
Joseph Devietti is an Associate Professor in the Department of Computer & Information Science at the University of Pennsylvania. His research focuses on improving programmability and performance of multiprocessor systems through architectural and programming model innovations. He actively advises PhD students and has supervised numerous graduates now employed at leading tech companies and academic institutions. Education: PhD (2012), MS (2009) in Computer Science and Engineering from University of Washington; BSE (2006) in Computer Science and BA (2006) in English from University of Pennsylvania. Employment: Associate Professor (2020–present), Assistant Professor (2013–2020) at University of Pennsylvania; Principal Scientist & Co-founder at Cloudseal, Inc. (2018–2020). Devietti’s research spans computer architecture, parallel programming, and deterministic execution. Key areas include cache/memory optimization (prefetching, false sharing repair), GPU programming models (race detection, block-size independence), and hardware-software co-design for concurrency safety. His recent work addresses dynamic runtime prefetch tuning (RPG 2 ), online code layout optimization (OCOLOS), and intelligent BTB prefetching (Twig) for data center applications. His publications from 2024–2017 reveal trends in instruction/cache optimization (2024–2020), GPU determinism (2018–2017), and race detection (2018–2016). Awards include the 2024 Penn Engineering Ford Motor Company Award, Radhia Cousot Best Paper (2018), and IEEE Micro Top Picks recognition (2023, 2009, 2008). Scientific Awards : 2024 Penn Engineering Ford Motor Company Award Radhia Cousot Young Researcher Best Paper Award (SAS 2018) IEEE Micro Top Picks (2023, 2009, 2008) Intel Early Career Faculty Honor Program (2013) Intel Ph.D. Fellowship (2011) Advising : Supervised 15+ PhD/Master’s students with placements at Google, Microsoft, Amazon, NYU, and the United States Naval Academy. Collaborations : Works with industry leaders (NVIDIA, Facebook) and academic institutions (University of Washington, Penn).
Dr. Alexandra Fedorova is a Professor in the Department of Electrical and Computer Engineering at the University of British Columbia (UBC), with an Associate Member role in the Computer Science department. She leads the Systopia systems research group, focusing on system software design, memory/storage management, and accelerator-centric computing. Her work emphasizes performance optimization, energy efficiency, and hardware-software co-design. She holds a PhD from Harvard University (2006), where she researched operating system scheduling under Margo Seltzer. Prior to UBC, she was an Associate Professor at Simon Fraser University (2006–2015). Fedorova is a recipient of the Alfred P. Sloan Research Fellowship and the Anita Borg Early Career Award. She consults for MongoDB's storage engine team and collaborates with industry on storage and performance challenges. Her research spans tools like Non-sequitur for program trace visualization, studies on storage-class memory (e.g., Optane), and frameworks for GPU acceleration. Recent efforts include Sunstone (spatial accelerator scheduling) and ExtMem (application-aware memory management). Her work bridges low-level systems with high-performance computing needs. Key contributions include optimizing NUMA systems, improving storage engine performance, and exploring processing-in-memory architectures. Fedorova’s projects often involve open-source collaboration, reflected in her GitHub repositories such as vividperf and perf-logging , which support performance analysis tools.
Xiaojun Ruan is an Associate Professor in the Department of Computer Science at California State University, East Bay. He holds a Ph.D. in Computer Science from Auburn University (2011) and a B.E. in Computer Science and Technology from Shandong University (2005). His primary research focuses on energy-efficient systems, cloud computing optimization, storage systems, and security-aware resource management. He has extensive experience in thermal modeling, parallel I/O performance, and distributed deep learning frameworks. Dr. Ruan’s work emphasizes balancing energy efficiency, reliability, and performance in storage and cloud environments. Notable projects include DuoFS (hybrid storage system), energy-aware VM allocation strategies, and securing cloud infrastructure against co-residence attacks. His research bridges hardware-software co-design principles with practical system optimizations. His publications span topics from NVMe SSD performance optimization to text augmentation for spam detection, reflecting a blend of storage systems and machine learning applications. He has actively contributed to improving Shuffle I/O in big data processing, thermal management in clusters, and secure virtualization techniques. Dr. Ruan collaborates on interdisciplinary projects involving distributed computing, cybersecurity, and real-time systems. His lab focuses on deploying energy-efficient solutions while maintaining robust reliability, evidenced by over 50 peer-reviewed articles and ongoing contributions to academic conferences.
Juan Manuel Cebrian Gonzalez is an Assistant Professor at the Department of Computer Engineering and Technology, Faculty of Informatics, University of Murcia. His work focuses on computer architecture, parallel systems, and energy-efficient computing. Doctorate: University of Murcia (2011), thesis on fine-grain power and thermal management in multicore processors. Research interests: Designing architectural mechanisms for optimizing power consumption and thermal management in multicore systems, cache coherence in parallel architectures, and vectorization techniques for high-performance computing. His work also explores heterogeneous architectures, fault tolerance, and efficient memory systems. Recent article trends: Focus on cache management, speculative execution, lock-free constructs, and performance-energy trade-offs in edge and heterogeneous computing. Key methodologies include gem5 simulation, Arm SVE, and AVX-512 vectorization. Collaboration: Supervised by Dr. Juan Luis Aragón Alcaraz and Dr. Stefanos Kaxiras. Active in the Computer Architecture and Parallel Systems research group.
Rakesh Kumar is an Associate Professor in the Department of Computer Science (IDI) at the Norwegian University of Science and Technology (NTNU) , affiliated with the Computer Architecture Lab (CAL) within the Faculty of Information Technology and Electrical Engineering . Prior to joining NTNU, he held postdoctoral and research associate positions at Uppsala University and the University of Edinburgh, and interned at Intel Barcelona Research Center. Research Interests include improving large-scale datacenter efficiency through microarchitecture and memory system optimizations, hardware/software co-designed processors, dynamic code translation, vectorization, and serverless function execution. His work explores ready-aware instruction scheduling, branch prediction organization, and address translation mechanisms. Scientific Contributions span publications at top-tier conferences like MICRO (2024, 2023, 2018, 2016) HPCA (2020, 2019, 2023, 2022) ASPLOS (2018) DATE (2019, 2021) Journal articles appear in ACM Transactions on Computer Systems and IEEE Computer Architecture Letters . Awards include Intel Spontaneous Level II/Excellence Award (2014) Best Presentation Award at HiPC-SS08 (2008) Best Paper Award at National Conference on High Computing Technologies (2008) Distinguished Artifact Award at MICRO 2023 PhD Supervision involves advising students like Roman Kaspar Brunner, Elias Orrem, and Truls Asheim on topics spanning microarchitecture, vector units, and runahead execution policies.
Pejman Lotfi-Kamran is an Associate Professor at the School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, where he also serves as the head of the school and director of Turin Cloud Services. His research focuses on computer architecture, systems, approximate computing, and cloud computing, with an emphasis on performance and energy efficiency for big-data applications. His educational background includes: Ph.D. in Computer Science, EPFL (2013) M.Sc. in Electrical and Computer Engineering, University of Tehran (2005) B.Sc. in Electrical and Computer Engineering, University of Tehran (2002) Lotfi-Kamran's research spans computer architecture innovations, including data and instruction prefetching, networks-on-chip, coherence protocols, and many-core processor design. He has pioneered work on scale-out processors, neural acceleration for GPUs, and approximate computing frameworks. His publications appear in top venues such as ISCA, HPCA, MICRO, and IEEE/ACM journals. His recent articles reflect a strong trend in improving system performance through intelligent prefetching, efficient NoC designs, and energy-aware architectures. Key themes include reducing frontend bottlenecks, optimizing cache behavior, and enhancing data delivery in large-scale systems. His work often combines cross-stack insights with hardware-software co-design for real-world impact. Scientific awards and recognitions include: 2017 CADS Best Paper Award 2016 Young Faculty Award from Iran's National Elites Foundation 2012-2013 Intel Ph.D. Fellowship 2012 and 2011 HiPEAC Paper Awards 2011 HPCA Best Student Paper Finalist Multiple academic honors from University of Tehran He has advised several graduate students including Paria Darbani, Ali Ansari, Mohammad Bakhshalipour, and Farid Samandi, many of whom have co-authored significant papers. His teaching spans institutions like Sharif University of Technology, Iran University of Science and Technology, and EPFL, covering advanced computer architecture and multiprocessor systems. He has led research projects such as AxBench and CloudSuite on Simics, and contributed to national initiatives like Iran’s National Grid. He is actively involved in tool development and continues to shape research in next-generation computing systems. He leads the Turin Cloud Services initiative at IPM and is deeply engaged in both theoretical and applied aspects of computer systems research, with ongoing work in neural acceleration, approximate computing, and scalable architectures.
Yale N. Patt serves as Professor of Electrical and Computer Engineering, holding the Ernest Cockrell, Jr. Centennial Chair in Engineering and recognized as a University Distinguished Teaching Professor at The University of Texas at Austin's Cockrell School of Engineering. His academic career spans decades with continuous teaching activity through Fall 2024 and Spring 2025 semesters. Professor Patt's research focuses on computer architecture and high-performance computing systems, specifically targeting innovations five to ten years beyond current industry capabilities. His philosophy emphasizes producing foundational knowledge for future technology development while educating students who will design tomorrow's computing systems. His work spans computer architecture, systems and networking, with particular focus on high performance substrate and microarchitecture design. His research group HPS (High Performance Systems) has made significant contributions to memory systems, branch prediction, and parallel computing architectures. Professor Patt's publications reveal consistent focus on fundamental computer architecture challenges, particularly addressing memory systems, branch prediction mechanisms, and performance optimization techniques that enable future computing systems. His work bridges theoretical innovation with practical application requirements. His exceptional contributions have been recognized with numerous prestigious awards: 2014 - Member, National Academy of Engineering 1996 - IEEE/ACM Eckert-Mauchly Award 2016 - Benjamin Franklin Medal, Franklin Institute 2000 - ACM Karl V. Karlstrom Outstanding Educator Award 1995 - IEEE Emanuel R. Piore Award 2013 - IEEE Harry H. Goode Award 1999 - IEEE Wallace W. McDowell Award 2011 - IEEE B. Ramakrishna Rau Award 2005 - IEEE Charles Babbage Award 2017 - Friar Centennial Teaching Fellowship (the highest teaching award at UT Austin, with recognition as the only Engineering professor to win it in the last 25 years) Professor Patt has mentored numerous PhD students throughout his career and co-authored the influential textbook 'Introduction to Computing Systems: From Bits and Gates to C and Beyond' (3rd edition, 2019). His teaching philosophy emphasizes deep understanding of computing fundamentals, reflected in his 'Ten Commandments for good teaching.' He has developed foundational courses including EE460N (Computer Architecture), EE306, and EE382N.19 (Microarchitecture), with teaching records dating back to at least 2000. He leads the High Performance Systems research group, which continues to advance computer architecture research while training the next generation of computer engineers. Workshops celebrating his 75th birthday in 2014 ('Yale@75') and 80th birthday in 2019 ('Yale:80-in-2019') demonstrate the global respect he has earned in the computer architecture community.
Alberto Ros is a Full Professor at the University of Murcia , Spain, in the Computer Engineering Department (DITEC) . His work focuses on cache coherence , memory hierarchy designs , memory consistency , and processor microarchitecture , with over 100 peer-reviewed publications. Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh , and held postdoctoral positions at the Technical University of Valencia and Uppsala University . He is an IEEE Senior Member . Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance. Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols. Scientific awards : Inducted into the MICRO Hall of Fame ISCA Hall of Fame 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS) Winner, ML-based Data Prefetching Competition Winner, 1st Instruction Prefetching Championship IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable) Best paper awards at HiPC'16, FORTE'16 Honorable mention at HPCA'24 Nomination at ISCA'22 Grants as Principal Investigator include ERC Proof of Concept (2023) ERC Consolidator (2018) Europe Excellence (2018) Seneca Foundation, Young Leaders in Research (2014) . Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.
Changhee Jung is the Samuel D. Conte Associate Professor in the Department of Computer Science at Purdue University. His research focuses on compilers and computer architecture with an emphasis on performance, reliability, and security. His educational background includes a Ph.D. from Georgia Tech (2013) under the supervision of Prof. Santosh Pande. Professor Jung's research spans compilers and computer architecture with a focus on performance, reliability, and security. He has developed program analysis and microarchitecture optimization techniques for soft error resilience, concurrency bug detection, and system security such as memory safety and Linux kernel permission check. Currently, he is working on energy-efficient intermittent computation and nonvolatile memory crash consistency. He often leverages compiler-architecture codesign and repurposes existing hardware features to develop cost-effective solutions for complex computing challenges. His recent publications demonstrate a clear trajectory toward intermittent computing systems, nonvolatile memory architectures, and security mechanisms for energy-constrained environments. His work shows innovative approaches to power failure recovery, capacitor vulnerability exploitation, and EMI attack defense in intermittent systems, with significant contributions to whole-system persistence, cache design, and prefetching techniques for low-power computing. His notable scientific achievements include: NSF CAREER Award (2018) Inducted into MICRO Hall of Fame (2021) Best Paper Honorable Mention in ISCA 2025 Memorable Paper Award Finalist in NVMW 2024 Dissertation Advisor of 2023 ACM SIGBED Paul Caspi Memorial Dissertation Award winner Jongouk Choi 2017 AMD Faculty Research Award Professor Jung has successfully advised numerous graduate students, many of whom have secured prominent positions at leading technology companies including Google, Intel, and Samsung Electronics. His lab, the CompArch (Compiler and Architecture) research group, was formed in 2013 at Virginia Tech and continues at Purdue, focusing on compiler-architecture cooperation to address cross-cutting concerns involving performance, reliability, and security. The lab has received significant research funding, including an NSF CAREER Award in 2018 and an AMD Faculty Research Award in 2017.
Laura Brown is an Associate Professor of Computer Science and serves as the Associate Dean of Data Science Initiatives in the College of Computing at Michigan Technological University. She also directs the Data Science M.S. and B.S. programs. Her educational background includes: PhD in Biomedical Informatics from Vanderbilt University MS in Biomedical Informatics from Vanderbilt University MSE in Electrical Engineering and Computer Science from the University of Michigan BS in Engineering from Swarthmore College Laura's research centers on Artificial Intelligence , Machine Learning , and Data Science , with applications spanning energy systems (microgrids and power systems), health informatics , and computer systems . Her work bridges theoretical advancements with real-world problem solving, particularly in optimizing electrical grids and healthcare through data-driven approaches. Her recent publications (2017-2019) demonstrate a strong focus on applying machine learning to energy forecasting and computer architecture. Key trends include solar irradiance prediction, load forecasting for power systems, and memory management in data centers using neural networks and dynamic policies. Laura actively mentors students as co-advisor for Women in Computing Science (WiCS) and organizes Carpentries workshops, ICPC programming competitions, and Google research workshops. Her grant portfolio includes significant funding from NSF ($1.6M+), Google ($53K), and DoD (~$1M) for projects in smart grid technologies, microgrid management, and computer science education. She collaborates through the Institute of Computing and Cybersystems (ICC), Ecosystem Science Center (ESC), and Center for Agile Interconnected Microgrids (AIM) on interdisciplinary research initiatives.
Ken Salem is a Professor at the Cheriton School of Computer Science, University of Waterloo. His research focuses on database systems, distributed systems, cloud computing, and storage management. He has supervised 12 PhD students to completion, with graduates now working at companies like Google, Qualcomm, and SAP. His research interests include: Database system architecture and optimization Distributed transaction processing Cloud-based data management Energy-efficient computing Storage systems and hardware interactions Recent publications show strong focus on transactional systems, durability mechanisms, and cloud-native database architectures. His work consistently appears in top-tier venues like VLDB, SIGMOD, and IEEE Transactions on Knowledge and Data Engineering. Key projects include: SHADOW systems for high availability DimmStore for memory power optimization NoSE for NoSQL schema design RemusDB for transparent database availability
Alan J. Smith is a Professor in the Electrical Engineering and Computer Sciences department at the University of California, Berkeley, within the College of Engineering. With a distinguished career spanning several decades, he has made significant contributions to computer architecture, system performance analysis, and memory systems. Dr. Smith received his S. B. from MIT and a Ph.D. from Stanford University. His educational background provided the foundation for his extensive research in computer systems. Professor Smith's research focuses on computer architecture and engineering, particularly in system performance analysis, I/O systems, cache memories, and memory systems. His work has profoundly influenced how computer systems are designed and evaluated, with particular emphasis on optimizing storage systems, cache performance, and energy efficiency in computing platforms. His research has bridged theoretical analysis with practical implementation, resulting in numerous influential publications and real-world applications. His publication record shows a consistent focus on computer system performance, evolving from early work on cache memory and paging algorithms to more recent research on multimedia workloads, energy management, and storage systems. The breadth of his work spans fundamental computer architecture principles to applied system design, with particular emphasis on measurement-based analysis and optimization techniques. Harry Goode Award of the IEEE Computer Society (2006) IEEE Reynold B. Johnson Information Storage Systems Award (2008) A. A. Michelson Award of the Computer Measurement Group (2003) Fellow of the American Association for the Advancement of Science (2001) Fellow of the ACM (2000) Fellow of the IEEE (1988) Throughout his career, Professor Smith has actively contributed to the academic community through editorial roles, conference organization, and professional society leadership. He has served as Subject Area Editor for the Journal of Parallel and Distributed Computing since 1989, chaired ACM SIGARCH and SIGOPS, and participated in numerous technical committees. His research has been supported by various grants that enabled extensive experimental work and system development. Professor Smith has been instrumental in developing benchmarking methodologies and performance analysis techniques that have become standard practices in computer system evaluation. His work on cache memory systems, in particular his influential 1982 Computing Surveys paper "Cache Memories," has shaped the field for decades.
