Dr. Vladimir Vlassov is a full Professor in Computer Systems at the Division of Software and Computer Systems (SCS) , Department of Computer Science (CS) , School of Electrical Engineering and Computer Science (EECS) , KTH Royal Institute of Technology , Stockholm, Sweden. He leads the AVA project in ALEC2, an AI-powered system for mental health care. He is a member of the Distributed Computing research group (DC@KTH) . Education & Roles: Holds a PhD and is a member of ACM and IEEE. Previously visited MIT (1998) and UMass Amherst (2004). Teaches courses on Data Mining , Distributed Systems , and Concurrent Programming . Research Interests: Focus on scalable AI, Cloud computing, distributed systems, and NLP for mental health. Projects include ExtremeEarth (Copernicus data analytics) and EMJD-DC (distributed computing PhD program). Grants & Projects: Principal Investigator in ALEC2 (adaptive mental health care) and ExtremeEarth (EU H2020). Led EU projects like ENCORE (manycore systems) and PaPP (embedded systems). Labs & Teams: Directs the Distributed Computing group, contributing to Hopsworks (machine learning feature store) and Maggy (hyperparameter optimization).
Sebastian Maier is a Researcher at the Department of Computer Science 4 (Distributed Systems and Operating Systems) at Friedrich-Alexander-University Erlangen-Nuremberg, part of the Faculty of Engineering. His work focuses on invasive computing, many-core architectures, and distributed systems. He has contributed to projects like the iRTSS (Invasive Run-Time Support System) and the OctoPOS kernel, emphasizing system software for resource arbitration and latency-aware systems. Maier has taught courses such as System-level Programming in C and Operating Systems exercises from 2013 to 2019. His research interests include hardware-software co-design, embedded systems security, and runtime systems for future architectures. He has advised students on thesis topics like distributed TCP/IP stacks and asynchronous communication interfaces in many-core systems. His recent work explores dynamic hardware-managed queues (DySHARQ) and resource arbitration mechanisms for tile-based architectures. These efforts aim to optimize parallel processing and real-time performance in embedded systems. Maier has also collaborated on latency-aware operating systems (LAOS) and security in embedded systems (SESES). Key Projects: iRTSS, AAM (Asynchronous Abstract Machines), SHARQ, LAOS Lab/Teams: Part of the Invasive Computing SFB/TRR 89 project (Project C1) His publications span conferences like ROME, ROSS, and HiPEAC, addressing challenges in many-core kernel design, scalability, and hardware-accelerated systems. Current research trends focus on adapting system software to heterogeneous and dynamic many-core environments.
Jonathan Balkind is an Assistant Professor in the Department of Computer Science at the University of California, Santa Barbara (UCSB). His research focuses on the intersection of computer architecture, programming languages, and operating systems, with an emphasis on pragmatic system design and open-source hardware. He leads the ArchLab at UCSB and is affiliated with the OpenPiton project, an open-source manycore research framework. Education includes a PhD and MA in Computer Science from Princeton University (adviser: Prof. David Wentzlaff), an MSci in Computing Science from the University of Glasgow (advisers: Prof. Joseph Sventek and Dr. John O'Donnell), and exchange studies at UCSB. His work has been supported by awards such as the NSF Early CAREER Award (2023) and the Open Hardware Trailblazer Fellowship (2022). Research interests span heterogeneous computing, cache-coherent systems, FPGA integration, and domain-specific architectures. Notable projects include the 25-core Piton chip, the CIFER SoC with embedded FPGA, and the DECADES manycore processor. Recent publications address fused-kernel operating systems (Stramash), control logic synthesis, and hyperloop data-center architectures. His awards reflect contributions to open-source hardware and academic mentorship, including Siebel Scholarship (2018), Gordon Y.S. Wu Fellowship (2013–2017), and multiple teaching/research recognitions. He actively collaborates with industry (e.g., Microsoft Research, ARM) and advises on open-source projects.
Miquel Moreto Planas is a Senior Lecturer in the Department of Computer Architecture at the Barcelona School of Informatics, Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing. His academic profile is deeply rooted in computer architecture and high-performance computing, with a strong emphasis on practical and theoretical advancements in multicore systems, memory management, and hardware acceleration. His research interests span a wide range of topics including computer architecture, high-performance computing, multicore and manycore systems, cache and memory management, hardware acceleration for genomics and AI, RISC-V processor design, processing-in-memory, interconnection networks, and real-time systems. These interests are reflected in his extensive publication record and collaborative projects. The most recent articles highlight a significant trend toward interdisciplinary research, particularly the application of advanced computer architecture techniques to bioinformatics and healthcare. Key themes include the acceleration of genomic sequence alignment using novel hardware such as processing-in-memory, the development of benchmarks for ARM-based HPC systems in genomics, and the creation of AI-based 3D decision support tools for neurosurgical applications. His work also continues to advance core computer architecture topics like cache management, power-aware resource allocation in heterogeneous systems, and the design of secure, post-quantum cryptographic hardware based on RISC-V. Fulbright Award 2011 HiPEAC Paper Award HiPEAC Paper Award 2024 HiPEAC Paper Award Moreto has been a principal investigator or key contributor to multiple competitive R&D+i projects, such as the STRATUM project for neurosurgical tools, REDIOH for open hardware, and the Laboratorio Zettaescala de Barcelona. He has advised several doctoral students, including López, G., Kostalampros, I., and Haghi, A., and is a core member of the CAP (High Performance Computing) research group at UPC. His work is characterized by strong collaborations with leading researchers like Mateo Valero, Eduard Ayguadé, and Jesús Labarta, often bridging the gap between UPC and BSC-CNS. His laboratory and team affiliations are centered around the CAP group and the Barcelona Supercomputing Center, where he contributes to cutting-edge research in high-performance and embedded computer architectures. His recent work on the BIMSA accelerator and the STRATUM project demonstrates a clear future direction toward applying high-performance computing solutions to critical problems in genomics and medicine.
Dr. Ke (Cory) Wang serves as Assistant Professor at the University of North Carolina at Charlotte in the Department of Electrical and Computer Engineering, where he conducts research in computer architecture and parallel systems. Ph.D. in Computer Engineering (2022), George Washington University M.Sc. in Electrical Engineering (2015), Worcester Polytechnic Institute B.Sc. in Computer Science (2013), Peking University His research focuses on machine learning-enabled computer architecture with emphasis on network-on-chip design , domain-specific accelerators , and cross-layer optimization for manycore systems. Specific areas include anomaly detection, graph neural network acceleration, and fault-tolerant communication frameworks. Recent publications demonstrate increasing integration of deep learning techniques with traditional architecture design, particularly for graph convolutional networks and heterogeneous systems . His work addresses multi-objective optimization across performance , energy efficiency , and security dimensions . Key scientific recognitions include: National Science Foundation award (CSR: Small: Cross-layer Design, 2023) National Science Foundation award (CRII: SHF: Flexible Design Framework, 2023) Dr. Wang leads the Intelligent Computer Architecture & Systems Laboratory , which develops advanced frameworks for network-on-chip optimization and AI-driven system design.
David Lopez Vilariño is a **Professor** at the **University of Santiago de Compostela**, affiliated with the **Department of Electronics and Computing** within the **Faculty of Physics**. He earned his PhD in 2001 with a thesis titled *"Active contours at the pixel level: design and implementation on cellular network architectures,"* advised by Dr. Diego Cabello Ferrer. His research focuses on **Computer Architecture**, **FPGA Acceleration**, **LiDAR Data Analysis**, and **Embedded Systems**, with notable contributions to LiDAR-based applications in urban planning, infrastructure monitoring, and medical imaging. He is part of the **ARQCOMP (Computer Architecture)** and **Artificial Vision** research groups. His work spans topics such as high-performance computing, parallel processing, and hardware optimization for vision-capable systems. Key projects include developing FPGA-based solutions for real-time video surveillance, retinal vessel analysis, and autonomous navigation systems. Publications emphasize **LiDAR data processing**, including algorithms for road detection, power line characterization, and 3D point cloud analysis. He also pioneered tools like the *Open Lidar Visualizer and Analyser* for 3D stereoscopic visualization. His expertise bridges hardware design and software development, particularly in leveraging FPGAs for embedded vision systems. No scientific awards or grants are explicitly listed, but his prolific publication record highlights sustained innovation in computer vision and geospatial technologies. His research team collaborates on projects involving manycore systems, GPU acceleration, and reconfigurable computing architectures.
Olaf Schenk is a Professor at the Institute of Computing within the Faculty of Informatics at Università della Svizzera italiana (USI), Switzerland. He serves as Director of the Institute of Computing and Co-Director of the Master in Computational Science. He is also an adjunct member of the Computer Systems Institute at USI. PhD in Information Technology and Electrical Engineering, ETH Zurich (2001) Venia Legendi in Mathematics and Computer Science, University of Basel (2009) Applied Mathematics, Karlsruhe Institute of Technology (KIT), Germany His research focuses on high-performance computing , computational science and engineering , and applied algorithms for extreme-scale simulations. He bridges computer science with scientific computing needs, particularly in parallel algorithms , sparse solvers , graph analytics , and manycore architectures . His work emphasizes scalable software tools and programming models for emerging HPC systems. The 15 most recent publications reflect a consistent focus on sparse matrix computations , parallel and task-based algorithms , graph partitioning , and performance optimization for heterogeneous and manycore systems. Keywords span high-performance computing, numerical linear algebra, and large-scale data analysis, showing strong integration of theoretical algorithm design with practical implementation. Olaf Schenk has received several prestigious honors: Elected Fellow, Society for Industrial and Applied Mathematics (SIAM) Senior Member, IEEE and ACM SIAM Supercomputing Prize 2023 IBM Faculty Award Two Leadership Computing Awards from the U.S. Department of Energy He has held leadership roles as Chair, Vice Chair, and Program Director of the SIAM Activity Group on Supercomputing. He serves as Associate Editor for ACM Transactions on Mathematical Software and on the editorial board of SIAM Journal on Scientific Computing . He has participated in over 60 international program committees, including top-tier conferences such as SC, IPDPS, and IEEE CSE. He advises PhD and Master’s students in computational science and leads research projects funded by national and international agencies. He is also the Founder & Director of Panua Technologies Sagl, focusing on high-end software for simulation and optimization. His research group at USI works on next-generation computing tools for extreme-scale scientific simulations, with ongoing work in adaptive algorithms, resilience, and hybrid CPU-GPU computing. He leads collaborative projects with institutions in Europe and the U.S., aiming to develop scalable, robust, and efficient software for future exascale systems.
Dr. Muhammad Shahbaz is the Kevin C. and Suzanne L. Kahn New Frontiers Assistant Professor in Computer Science at Purdue University. He specializes in designing domain-specific abstractions, compilers, and architectures for emerging workloads such as machine learning and self-driving networks. His research bridges networking, machine learning, and computer architecture to create high-performance, scalable systems. Shahbaz holds a Ph.D. and M.A. in Computer Science from Princeton University and a B.E. in Computer Engineering from the National University of Sciences and Technology (NUST). Before joining Purdue, he conducted postdoctoral research at Stanford University and worked as a Research Assistant at Georgia Tech and the University of Cambridge. His research interests include Networking and Operating Systems, Artificial Intelligence, Machine Learning, Computer Architecture, Distributed Systems, and Programming Languages/Compilers. He has developed influential open-source systems like Pisces, SDX, and NetFPGA-10G, which are widely adopted in industry and academia. Shahbaz has received prestigious awards including the Facebook, Google, and Intel Research Awards; IETF/IRTF ANRP Prize; ACM SOSR Systems Award; and APNet Best Paper Award. His work focuses on advancing edge computing, smartNICs, in-network machine learning, and scalable distributed systems. His research portfolio includes contributions to network caching, hardware acceleration, and AI-driven network optimization. He leads projects like CAREER (per-packet AI on heterogeneous data planes) and EdgeScaler (smart auto-scaling for 5G edge networks). His systems address challenges in tail latency, resource harvesting, and scalable multicast in modern networks.
Shervin Hajiamini is an Assistant Professor of the Practice of Computer Science at Vanderbilt University's School of Engineering. He holds a Ph.D. from Washington State University, an M.Sc. from Delft University of Technology, and a B.Sc. from Azad University. His research focuses on green computing, particularly energy efficiency in multi-core systems, including dynamic voltage/frequency scaling (DVFS), voltage-frequency islands (VFI), and task scheduling optimizations. Recent work explores energy efficiency through heuristic algorithms, stochastic models, and dynamic programming frameworks. His articles (2015–2023) emphasize energy-time tradeoffs, cache optimization, and power-aware scheduling in multi-core architectures. No scientific awards are explicitly listed. His advising and grants sections are currently empty. He is affiliated with the School of Engineering's Computer Science department at Vanderbilt University.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and the founder and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research and Technology – Hellas (FORTH) in Heraklion, Crete, Greece. He has held academic positions since 1986 and played a pivotal role in establishing the Computer Science Department at the University of Crete. His research spans computer architecture, interconnection networks, VLSI systems, and high-performance computing, with a strong focus on scalable, low-power, manycore systems and RISC-V. He has led numerous European R&D initiatives, including serving as Coordinator of the ExaNeSt project. PhD in Computer Science, University of California, Berkeley (1983) MSc in Electrical Engineering and Computer Science, University of California, Berkeley (1980) Diploma of Electrical Engineering, National Technical University of Athens (1978) Manolis Katevenis's research focuses on advancing scalable system architectures for high-performance and big data computing. His work in computer architecture includes RISC-V, exascale computing, and manycore systems. He has made foundational contributions to interprocessor communication, particularly through remote-write, remote-DMA, and remote-enqueue mechanisms, and has pioneered innovations in interconnection networks and low-latency network interfaces. His research integrates hardware and software co-design to optimize performance, energy efficiency, and scalability in large-scale computing systems. The recent publications highlight a strong trend in exascale computing, interconnection networks, and FPGA-based prototyping of manycore systems. His work emphasizes scalable, low-power architectures, with recurring themes in congestion management, fair scheduling, crossbar design, and hardware-software integration for HPC. The articles span high-impact journals such as IEEE/ACM Transactions on Networking, IEEE Micro, and Computer Networks, reflecting sustained contributions to computer architecture and networking. ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981–1983) Greek State Fellowship (1973–1978) Stelios Pichoridis Award for Outstanding University Teaching (2015) Member of Academia Europaea (elected 2012) Award by the Secretary General of the Region of Crete (2003) IEEE Milestone recognition for the RISC Project (2015) Manolis Katevenis has supervised over 50 graduate theses and mentored many prominent Greek computer architects, including recipients of the ACM Maurice Wilkes Award. He has served as Principal Investigator or co-PI in over 30 R&D projects with a total budget exceeding 18 million euros, including major European initiatives such as ExaNeSt (which he coordinated), EuroEXA, EcoScale, SARC, ENCORE, and multiple HiPEAC Network of Excellence projects. His leadership extends to project coordination, architectural design, FPGA prototyping, and systems software development. Katevenis founded and leads the CARV Laboratory at FORTH-ICS, a major research team with 80–100 members focused on computer architecture and VLSI systems. The lab has spun off the Distributed Computing Systems (DCS) Laboratory and is central to European exascale computing efforts, including participation in the European Processor Initiative. CARV has developed large-scale prototypes such as the 768-core ExaNeSt system and the Formic FPGA platform for manycore research.
Mats Brorsson is a Professor at the Division of Software and Computer Systems , KTH Royal Institute of Technology. His research spans multiple areas of computer architecture and parallel computing, with a focus on system software, energy-aware architectures, and performance debugging tools. He is actively involved in projects like the PaPP ARTEMIS collaboration and coordinates the KTH-SICS Scalable Computing Systems initiative. Research Interests : Mats Brorsson's work primarily addresses parallel computing , task-based programming models (e.g., OpenMP), and energy-efficient computer architectures . He has made significant contributions to NUMA system optimization , work-stealing schedulers , and runtime systems for high-performance computing. Professional Activities : Mats Brorsson serves as coordinator for the PaPP ARTEMIS project and is a member of the KTH-SICS Collaboration in Scalable Computing Systems. His publications reflect deep engagement with task scheduling , cache coherence protocols , and adaptive resource management for parallel systems.
PD Dr. Josef Weidendorfer is a qualified private lecturer at Technische Universität München (TUM) and leads the Future Computing Group at the Leibniz Computing Centre (LRZ). He holds a dual affiliation with TUM's Department of Informatics, Chair of Computer Architecture and Parallel Systems (Prof. Schulz), and the Leibniz Rechenzentrum der Bayerischen Akademie der Wissenschaften. His work focuses on developing smooth migration strategies for future HPC systems and evaluating novel technologies to improve system-level and workload analysis tools. Weidendorfer's research interests encompass Parallel Computer Architectures, High Performance Computing, Multi-/Manycore architectures, GPGPU, Performance analysis and optimization, Cache Simulation, Virtual Machines, and dynamic code generation. He is particularly interested in strategies for improving computational efficiency across various hardware structures, including specialized accelerator hardware for HPC codes. He regularly organizes the UCHPC workshop (since 2010 with Euro-Par) about unconventional hardware for HPC computing and is co-organizer of the PSTI workshop series. His recent publications reveal a strong focus on HPC system optimization, with particular emphasis on load balancing techniques, cache partitioning, application malleability, and performance monitoring. The research trajectory shows increasing attention to practical implementation challenges in modern heterogeneous computing environments, especially regarding GPU utilization, resource partitioning under power constraints, and phase-aware system monitoring. Weidendorfer maintains the open-source tools Callgrind/KCachegrind for cache simulation and has supervised numerous student projects across bachelor's, master's, and guided research programs. He teaches courses including Virtualization Techniques, Parallel Programming Systems, and Advanced Computer Architecture, demonstrating strong commitment to both research and education in computer architecture and parallel systems. As principal investigator for multiple large-scale projects including EU Project SEANERGYS (2025-2028) and BMBF Project ScalNext (2022-2025), he leads significant research initiatives focused on future computing technologies and HPC system development.
Adrian Sampson is an Associate Professor in the Department of Computer Science at Cornell University, where he is part of the Computer Systems Laboratory and the programming languages group. He joined Cornell in 2016 as an Assistant Professor and was promoted to Associate Professor in 2022. Prior to Cornell, he was a Visiting Researcher at Microsoft Research (2015-2016). He received his Ph.D. from the University of Washington in 2015 under advisors Luis Ceze and Dan Grossman, with a dissertation on Hardware and Software for Approximate Computing. His research focuses on breaking down abstraction barriers and rethinking the hardware-software interface. He is particularly known for his work on approximate computing, which explores how computers can be more efficient by allowing them to make controlled mistakes. He leads the Capra research group at Cornell, which investigates programming languages and computer architecture. Sampson's recent publications demonstrate a strong focus on hardware acceleration, FPGA programming, compiler design, and programming language theory. His work often bridges the gap between high-level programming abstractions and low-level hardware implementation, with particular attention to predictability, verification, and energy efficiency. He has made significant contributions to geometry types for graphics programming, timeline types for modular hardware design, and virtual machines for FPGA programming. Among his notable recognitions are the IEEE TCCA Young Computer Architect Award (2021), NSF CAREER award (2019), and multiple Distinguished Artifact Awards at major conferences. He has advised numerous Ph.D. students who have gone on to positions at institutions like Wellesley College, Northwestern University, and Amazon. Sampson is actively involved in academic service, serving on program committees for major conferences including PLDI, ASPLOS, and ISCA. He has also held leadership roles such as ACM SIGARCH Board of Directors (2023-2025) and SIGPLAN Information Director. His teaching at Cornell includes courses on computer systems, programming languages, and advanced compilers.
Phil Howard serves as an Associate Professor in the Department of Computer Systems Engineering at Oregon Institute of Technology's Klamath Falls campus. With a Ph.D. in Computer Science from Portland State University (2012) and over 20 years of industry experience at Hughes Aircraft, Intel, Diamond Multimedia, and Sharp Microelectronics Technology, he bridges academic theory with real-world engineering practice. His visiting professorships at West Virginia University Institute of Technology (2013) and University of Puget Sound (2012) further demonstrate his cross-institutional academic engagement. His educational background includes: Ph.D. in Computer Science, Portland State University, 2012 Dr. Howard's research specializes in concurrent programming paradigms and high-performance data structures , with critical focus on memory models for multicore architectures. His work pioneers relativistic programming techniques to overcome synchronization bottlenecks in parallel systems. This research directly impacts operating system design, compiler optimization, and network programming frameworks where latency tolerance and scalability are paramount. His publication trajectory reveals a concentrated evolution from theoretical concurrency models (2012) toward implementable data structure solutions (2013), consistently targeting the synchronization challenges of modern manycore processors. This trajectory positions his work at the intersection of theoretical computer science and practical high-performance computing. As an educator, Dr. Howard teaches advanced systems courses including Compiler Methods, Operating Systems, and Concurrent Programming, leveraging his industry experience to contextualize complex concepts like grammars, network programming, and Linux systems development.
Jonas Rabenstein is a Researcher at the Department of Computer Science 4 (Distributed Systems and Operating Systems) within the Technische Fakultät at Friedrich-Alexander-Universität Erlangen-Nürnberg. His work focuses on invasive computing, distributed systems, and system software for many-core architectures. He contributes to the SFB/TRR 89 Invasive Computing project, particularly in developing the Invasive Runtime Support System (iRTSS). His research emphasizes resource arbitration, real-time systems, and embedded architectures. Research Interests: Rabenstein explores challenges in operating systems for heterogeneous hardware, virtual shared memory for MPSoCs, and scalable system software for future many-core processors. His projects address coherence management, task scheduling, and hardware-software co-design to optimize resource utilization. Teaching and Advising: He teaches System Programming courses and has advised multiple theses, including studies on relocating loaders for OctoPOS, system call frameworks, and distributed TCP/IP stacks for manycore systems. His supervision spans Bachelor's and Master's projects, emphasizing practical implementation of distributed and real-time systems. Affiliations: As part of the Distributed Systems and Operating Systems group, he collaborates on projects like OctoPOS and contributes to conferences such as HiPEAC and IPDPSW. His work bridges theoretical system design with practical deployment on emerging architectures.
