Jeyavijayan 'JV' Rajendran is an Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University, part of the College of Engineering. He is an ASCEND Fellow and leads the Secure and Trustworthy Hardware (SETH) Lab. His research focuses on hardware security, computer security, and novel applications of AI in secure hardware design. Education: PhD in Electrical Engineering (NYU 2015), MS in Computer Engineering (NYU Tandon 2010), BE in Electronics and Communication Engineering (Anna University 2008). Research Interests: Hardware Security, Computer Security, Logic Locking, Hardware IP Protection, and Reinforcement Learning for Security. He explores AI-driven approaches to detect vulnerabilities, protect intellectual property, and enhance secure hardware design through fuzzing, obfuscation, and formal verification. Notable Awards: 2022 Office of Naval Research Young Investigator Award, 2021 IEEE CEDA Ernest Kuh Early Career Award, 2017 NSF CAREER Award. Lab and Teams: The SETH Lab focuses on trustworthy hardware design, developing techniques to secure integrated circuits against reverse engineering and IP theft. Current projects include LLM-based hardware code generation, formal approaches for hardware fuzzing, and AI-driven vulnerability detection.










