Dr. Andrea Bastoni is a Postdoctoral Researcher and Research Fellow at the Chair of Cyber-Physical Systems in Production Engineering at Technical University of Munich (TUM), Faculty of Mechanical Engineering. He is also the CTO and co-founder of Minerva Systems , developing operating system solutions for AI-ready embedded applications. His expertise spans real-time operating systems, cyber-physical systems, and predictable system design for heterogeneous platforms. His research focuses on enhancing predictability of memory hierarchies in complex SoCs through techniques like memory bandwidth regulation and cache partitioning. This work has industrial applications in safety-critical domains such as avionics and railways, where he contributes to certifiable hypervisors and operating systems. As former Software Architect of the PikeOS hypervisor at SYSGO GmbH (2012-2020), he specialized in DO-178C, IEC 61508, and EN 50128 standards. His academic background includes a Ph.D. in Computer Engineering from the University of Rome Tor Vergata (2007-2011), where he developed LITMUS^RT as part of UNC's Real-Time Systems Group during a visiting researcher period (2009-2010). His publications reflect ongoing work on Multicore Real-Time Scheduling , Mixed-Criticality Task Isolation, and Arm DynamIQ shared unit analysis. He actively participates in program committees for conferences like RTSS, DSN, and DATE.
Prof. Dr.-Ing. Jürgen Teich is a full Professor and Chair for Hardware-Software Co-Design at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU). He serves as Head of Department Computer Science and Vice Dean of the Technical Faculty since August 2024, and has been Speaker of the FAU Research Center Embedded System Initiative (FAU ESI) since 2023. His educational background includes: Diploma degree in Electrical Engineering, University of Kaiserslautern (1989) Dr.-Ing. degree in Electrical Engineering, University of Saarland (1993) Habilitation (PD Dr.-Ing.) entitled "Synthesis and Optimization of Digital Hardware/Software Systems" (1996) Prof. Teich's research focuses on Embedded Systems , Invasive Computing , Hardware-Software Co-Design , and Reconfigurable Computing . His work spans from theoretical foundations to practical implementations, with particular emphasis on resource-constrained systems, many-core architectures, and energy-efficient computing. He has pioneered research in invasive computing paradigms that enable more efficient use of many-core processors by allowing applications to dynamically claim resources. His recent publications reveal a strong trend toward energy-efficient AI deployment on embedded devices , security of embedded systems , and novel memory technologies . There's a clear focus on practical implementations of machine learning on microcontrollers (TinyML), hardware acceleration for data processing, and innovative approaches to power management in self-powered systems. Among his notable scientific awards are: IEEE Fellow (since 2018) Member of Academia Europaea, Section Informatics (since 2011) Member of the National Academy of Science and Engineering (acatech) (since 2018) Member of the German Society of Humboldtians (since 2021) Prof. Teich has been Principal Investigator for numerous DFG-funded projects including SFB/Transregio 89 "Invasive Computing" (2010-2022), SFB 694, and multiple priority programs. He has coordinated large collaborative research efforts across Germany and internationally, with significant funding from DFG and other sources. His research group has produced influential work in embedded systems design and co-design methodologies. He leads the Hardware-Software Co-Design research group at FAU, which focuses on innovative approaches to embedded system design, invasive computing architectures, and efficient implementation of machine learning on resource-constrained devices. The group maintains strong collaborations with industry partners including Intel, Xilinx, and automotive companies.
Daniel Müller-Gritschneder is an Adjunct Teaching Professor (Privatdozent) at the Technical University of Munich (TUM), affiliated with the Chair of Electronic Design Automation. He leads the 'Electronic System Level' research group, focusing on embedded systems, TinyML, virtual prototyping, and hardware resilience. He temporarily served as head of the Chair of Real-Time Systems (2019–2020) and holds a senior membership in IEEE. His research spans: TinyML : Optimizing neural network inference for microcontrollers. Virtual Prototyping : Fast simulation for embedded software development (e.g., ETISS simulator). Runtime Verification : Hardware monitoring for safety-critical systems. Fault Tolerance : Cross-layer resilience against soft errors. Design Automation : NoC synthesis and RISC-V toolchain optimization. His publications emphasize RISC-V-based systems, TinyML deployment, fault injection, and embedded AI. Recent works show trends toward compiler-assisted security, thermal management, and automated design-space exploration for edge devices. Awards: Best Paper Award (SiPS 2019) Habilitation Award (Bund der Freunde der TUM, 2019) 2nd Best Paper (SMACD'15) Best Paper nominations at DAC'07, DATE'10, Analog'10, NOCS'13 He advises researchers in the Electronic System Level group and contributes to EU projects (e.g., Scale4Edge). His lab develops tools like ETISS, MLonMCU, and Seal5 for RISC-V and TinyML ecosystems.
Stefan Wildermann is a Professor at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), where he leads the Reconfigurable Computing Group within the Chair of Computer Science 12 (Hardware-Software Co-Design) in the Department of Computer Science. He has maintained continuous research activity at FAU since 2006, progressing from researcher to his current leadership position. Dr. Wildermann earned his Diploma degree in Computer Science from FAU in 2006 and completed his doctorate (Dr.-Ing.) in Computer Science at the same institution in July 2012. His academic career has been entirely rooted at FAU, demonstrating a strong institutional commitment and progression through the ranks. His research spans multiple cutting-edge areas in computer science and engineering, with particular emphasis on reconfigurable systems and hardware-software co-design. Wildermann's work in edge computing explores efficient processing at the network periphery, while his research in organic computing investigates self-organizing systems that can adapt to changing environments. His expertise extends to optimization techniques for embedded systems, applying game theory principles and convex optimization methods to solve complex resource allocation problems. More recently, he has integrated reinforcement learning approaches to enhance system adaptability and performance. His teaching portfolio includes courses on event-driven systems, computer engineering fundamentals, embedded systems, and hardware-software co-design. Analysis of Wildermann's publication record from 2021-2025 reveals a strong focus on hardware acceleration, security, and embedded systems. His work demonstrates consistent evolution from foundational research in reconfigurable architectures toward practical applications in IoT, robotics, and secure computing. A significant portion of his recent work addresses near-data processing using FPGAs for database acceleration, while maintaining parallel research streams in side-channel security analysis and energy-efficient embedded systems design. His publications frequently appear in top-tier conferences including DATE, FPL, ASP-DAC, and HOST, reflecting strong recognition within the computer architecture and embedded systems communities. Wildermann has held significant leadership roles including Head of the Reconfigurable Computing Group since 2015 and previously served as Head of the Self-organizing Systems Group (2012-2015) and Lab Leader of the Automotive Lab within the Embedded Systems Initiative (2016-2020). His research has been consistently funded through multiple projects investigating invasive computing, reconfigurable architectures, and embedded systems design methodologies. Currently based in Room 02.116 at Cauerstr. 11, 91058 Erlangen, Wildermann continues to lead active research in the Hardware-Software Co-Design group, supervising projects that bridge theoretical computer science with practical hardware implementation challenges.
Nele Mentens is a full professor at both KU Leuven and Leiden University, where she leads cutting-edge research in applied cryptography, hardware security, and secure embedded systems. At KU Leuven, she is affiliated with the Faculty of Engineering Technology and the Electrical Engineering Department (ESAT), leading the Emerging Technologies, Systems & Security (ES&S) research group at the Diepenbeek campus. Simultaneously, she holds a full professorship at Leiden University’s Leiden Institute of Advanced Computer Science (LIACS), focusing on applied cryptography and security. She has been instrumental in numerous national and international research initiatives, including Horizon Europe and NWO-funded projects. Full Professor, KU Leuven (since 2023) Full Professor, Leiden University (since 2020) Associate Professor, KU Leuven (2014–2023) Post-doctoral Researcher & Lecturer, KHLim / KU Leuven (2007–2014) Ph.D. in Engineering Science, KU Leuven (2007) M.Sc. in Electrical Engineering, KU Leuven (2003) Her research focuses on secure and efficient hardware design, particularly for cryptographic applications on FPGAs, reconfigurable architectures, IoT security, and neuromorphic computing. She explores physical attack resistance, side-channel analysis protection, and trusted computing architectures, with applications in healthcare, industrial monitoring, and endpoint AI. Her work bridges theoretical cryptography with practical hardware implementations, emphasizing energy efficiency and real-time performance. The 15 most recent publications reflect a strong trend toward secure, energy-efficient, and intelligent embedded systems. Topics include neuromorphic AI accelerators, trusted IoT architectures, dynamic reconfiguration for side-channel protection, and secure medical data processing. These works span disciplines such as computer architecture, cybersecurity, digital design, and embedded systems, with a focus on hardware-software co-design and real-world deployment. Nele Mentens has received recognition for her contributions, including: Best Paper Award, DATE'16 Best Paper Nomination, AsianHOST'17 Best Paper Award, CHES'19 She has supervised over 15 Ph.D. students and post-docs, both current and former, and has served as principal investigator in approximately 25 funded research projects. Her work has attracted significant grants from Horizon Europe, NWO, FWO, and national innovation programs. She actively contributes to the academic community through editorial roles in top journals and leadership in major conferences. Nele Mentens leads the ES&S research group at KU Leuven and collaborates closely with LIACS at Leiden University. Her team includes Ph.D. students, post-docs, and research experts working on projects like NimbleAI, NeuroSoC, and TrustedIoT. She has also established secure electronics labs through infrastructure grants and maintains strong international ties with institutions such as EPFL, Ruhr University Bochum, and ETH Zurich.
Prof. Dr. Andreas Herkersdorf is a Full Professor and Chair of Integrated Systems at the Technical University of Munich (TUM) School of Computation, Information and Technology. His research focuses on application-specific multicore processors (MPSoC), FPGA-based prototyping, fault-tolerant systems, and energy-efficient architectures, with applications in IP packet processing, automotive systems, and visual computing. He has received multiple IBM innovation awards and serves on editorial boards including the DFG Review Board for computer architecture. Education: Dipl.-Ing. Electrical Engineering (TUM, 1987), Dr. techn. Electrical Engineering (ETH Zurich, 1991) Research: MPSoC architectures, autonomic computing, NoC resilience, FPGA acceleration, and self-optimizing systems. Awards: IBM Master Inventor (1998), IBM Outstanding Technical Achievement Award (2001), multiple IBM Innovation Achievement Awards (1996-2003) His recent publications emphasize hardware/software co-design, machine learning integration for runtime optimization, and network-on-chip innovations. He collaborates on projects involving 6G systems, smartNICs, and automotive communication protocols.
Khalil Esper is a Researcher at the Department of Computer Science, Faculty of Engineering, Friedrich-Alexander-University Erlangen-Nuremberg (FAU), where he works at the Chair of Computer Science 12 (Hardware-Software Co-Design). His research focuses on verification, energy optimization, and runtime requirement enforcement in embedded systems and MPSoCs. His educational background includes: Informatics Engineering from Aleppo University, Syria (2010-2015) European Master in Embedded Computing Systems (EMECS) from Rhineland-Palatinate University of Technology Kaiserslautern-Landau (Germany) and Norwegian University of Science and Technology (Norway) (2017-2019) Esper's research interests center around verification and model checking, energy optimization on MPSoC, real-time systems and embedded systems, and autonomic computing. His work particularly focuses on runtime requirement enforcement mechanisms for non-functional properties in multi-processor systems-on-chip, with applications extending to medical devices and human-robot interaction systems. He has developed approaches using finite state machines, reinforcement learning, and evolutionary algorithms to ensure system properties are maintained during execution. His publication record shows a strong trend toward applying formal methods and runtime enforcement techniques to increasingly complex systems, with recent work expanding into safety-critical applications like orthoses and human-robot interaction. The interdisciplinary nature of his research bridges computer science, embedded systems engineering, and biomedical applications. Esper has supervised multiple theses including: Sascha H.: Runtime Requirement Enforcement of Non-Functional Requirements on MPSoCs Using Fuzzy Logic (2022) Iana S.: Feedback-Based Control of Non-functional Program Execution Properties on Linux (2023) Philipp L.: Runtime Requirement Enforcement of Functional and Non-Functional Requirements of a Knee Orthosis Based on a Digital Twin (2024) Avinash N.: Runtime Requirement Enforcement of Safety Properties of an Ankle Orthosis Based on a Digital Twin (2024) Zhiyi T.: Generation of Environment FSMs Using Machine Learning Techniques (2025) Moustafa A.: Runtime Requirement Enforcement of Safety Properties of Human-Robot Interaction Based on a Digital Twin (2025) Florian K.: Runtime Requirement Enforcement of Safety Properties of Human-Robot Interaction (2025) He has been actively teaching courses on Approximate Computing and Embedded Systems since the 2021/2022 academic year, demonstrating his commitment to academic instruction alongside his research activities. Esper is involved in the InvasIC research project, part of the DFG Transregional Collaborative Research Center 89 on Invasive Computing, which explores novel approaches to resource management in parallel computing systems.
Tim Twardzik is a Researcher at the Chair of Integrated Systems within the School of Computation, Information and Technology at the Technical University of Munich . His work focuses on hardware acceleration techniques for Linux systems, particularly in optimizing inter-process communication (IPC), event notification mechanisms, and synchronization primitives through FPGA-based and MPSoC architectures. His research explores: Hardware-assisted scheduling for Linux Low-latency system-on-chip (SoC) design User-space event notification acceleration Thread synchronization mechanisms MPSoC-based embedded computing Performance analysis through simulation frameworks Publications highlight his contributions to hardware acceleration trends, with a focus on improving operating system primitives (e.g., futex, epoll) through custom silicon implementations.
Klajd Zyla is a PhD student and scientific assistant at the Chair of Integrated Systems, TUM School of Computation, Information and Technology, Technical University of Munich. His research focuses on architectures for flexible data packet processing in high-performance network cards, including NoC optimization, priority-aware scheduling, and RDMA acceleration. PhD Student at LIS (Chair of Integrated Systems), Technical University of Munich (since Jan 2022) Teaching: SystemC Laboratory (since SS 2022) His research investigates on-chip interconnects, packet scheduling with multiple priorities, and acceleration of transport protocols like RDMA for FPGA-based SmartNICs. Publications demonstrate expertise in crossbar architectures, deadlock avoidance, and resource management for MPSoCs. Supervised students include: Nour Abouelkheir (2D Mesh NoC design) Aleksa Stojkovic (HiPerNoC enhancement) Antra Pramanik (Packet-processing FPGA implementation) Arathi Anitha (Deadlock-avoidance algorithms) Johannes Ecker (Hardware schedulers comparison)
Prof. Timo Hönig is a Professor leading the Bochum Operating Systems and System Software (BOSS) Research Group at Ruhr-Universität Bochum (RUB). Previously, he served as an Assistant Professor at Friedrich-Alexander-University Erlangen-Nürnberg (FAU), where he was part of Department of Computer Science 4. His research focuses on Energy-Aware Computing Systems, Operating Systems, and System Software design with applications in embedded and real-time systems. Key research projects include the DFG Collaborative Research Center/TR 89 (Invasive Computing) and the DFG SPP 1914 (Latency- and Resilience-Aware Networking). He has received notable awards such as the SOSP SRC Gold Medal (2019) and the ISORC Best Paper Award (2017). He actively contributes to conferences like ACM EuroSys and USENIX ATC, and has led initiatives like the Albatross runtime system for energy-efficient HPC clusters. Teaching includes courses on Energy-Aware Computing and Operating Systems Technology. His work bridges theoretical system software design with practical applications in energy efficiency and heterogeneous architectures. The BOSS group explores future system software challenges for many-core and NVM-based systems.
Professor Anestis Terzis serves as a Professor of Digital Systems Design and Head of the Institute for Communication Technology (IKT) at Technische Hochschule Ulm within the Faculty of Electrical Engineering and Information Technology. He coordinates the International Electrical Engineering Program and is responsible for the Vehicle Systems specialization. His office is located in Room W2405 at Albert-Einstein-Allee 53-55, 89081 Ulm, Germany. Professor Terzis specializes in digital system design with focus on FPGA, VHDL, and high-level design methodologies. His research spans Camera Monitor Systems (CMS) for automotive mirror replacement, advanced camera-based driver assistance systems, vehicle electronics, digitalization in laboratory didactics, and autonomous driving technologies. He has pioneered work in digital mirror systems compliant with ISO 16505 standards and has contributed significantly to image processing for automotive applications. His publication record demonstrates consistent contributions to automotive imaging technology, with recent work focusing on image compression impacts on detection quality, CMS image quality parameters, and programmable processing for autonomous vehicles. Professor Terzis has edited the comprehensive Handbook of Camera Monitor Systems published by Springer, establishing himself as a leading authority in this specialized field. As Head of the Institute for Communication Technology, he leads research initiatives connecting digital systems design with automotive applications. He also serves as Coordinator for the Study with In-depth Practice program and is a member of the Institute for Vehicle System Technology (IFS), demonstrating his commitment to both theoretical advancement and practical implementation in automotive electronics.
Prof. Hans-Joachim Wunderlich is a Professor at the University of Stuttgart's Institute of Computer Architecture and Computer Engineering, within the Faculty of Computer Science, Electrical Engineering, and Information Technology. His research focuses on hardware reliability, fault tolerance, and testing methodologies for VLSI circuits and embedded systems. He specializes in areas such as delay fault testing under PVT variability, approximate communication, and aging-aware design. Key research interests include robust testing techniques for small delay faults, error-tolerant communication protocols (e.g., RAPPER and Gray code-based approaches), and GPU-accelerated simulation of faults. His work addresses challenges in functional safety, interconnect reliability, and securing reconfigurable architectures against security violations. He explores energy-efficient iterative solvers for approximate computing environments and develops methods for predicting device aging and early life failures. Prof. Wunderlich’s contributions span academic and industrial applications, with a focus on real-time systems and dependable multi-processor systems-on-chip (MPSoCs). His research integrates formal verification, machine learning for defect detection, and hybrid protection schemes for reconfigurable scan networks. Recent work emphasizes stress-aware testing strategies and optimization of sensor data streaming in resource-constrained environments.
Joachim Falk is a researcher at the Department of Hardware-Software Co-Design (Computer Science 12) at Friedrich Alexander University Erlangen-Nuremberg. With over 20 years of experience since joining the department in 2004, he specializes in electronic system level design, dataflow programming, and hardware-software co-design, contributing significantly to the field through publications, teaching, and research leadership. His educational background includes: Doctorate degree (Dr.-Ing.) in Computer Science from FAU (2014) Diploma degree in electrical engineering (data processing) from Georg-Simon-Ohm University of Applied Science Nuremberg (2002) Falk's research focuses on Electronic System Level Design, Hardware/Software Code Generation for Data-Flow Graphs, Compiler Optimizations, and Parallel Architectures. His work bridges theoretical computer science with practical embedded systems implementation, particularly through the SystemC framework and his contributions to the SysteMoC language. He actively explores energy-efficient computing approaches for dataflow networks and embedded systems, with recent work emphasizing self-powering networks, clock and power gating techniques, and multi-reader buffer implementations for heterogeneous architectures. His recent publication trends reveal a consistent focus on optimizing dataflow networks for energy efficiency and performance. Key themes include self-powering dataflow networks, innovative clock and power management techniques, buffer management strategies for heterogeneous many-core systems, and invasive computing approaches. His research demonstrates a strong connection between theoretical models and practical implementation challenges in embedded systems design. Dr. Falk teaches courses including 'Entwicklung interaktiver eingebetteter Systeme' (Development of Interactive Embedded Systems) for Winter Semester 2024/2025 and 'SystemC' for Summer Semester 2024, supervising multiple theses on security modeling at the electronic system level and sleep/wake-up strategies for hardware implementations of dataflow networks. His research is conducted within the framework of projects like SysteMoC (representation of computational models in SystemC) and SystemCoDesigner (design space exploration for embedded systems).
Prof. Jens Rettkowski is a leading academic specializing in advanced computing architectures, particularly focusing on multi-core systems, reconfigurable hardware (FPGAs), and networks-on-chip (NoC). His work bridges theoretical computer architecture with practical applications in embedded systems, real-time processing, and autonomous technologies. Research Interests: Multi-Core Architecture Design and Optimization Networks-on-Chip (NoC) for High-Performance Systems Reconfigurable Computing and FPGA-Based Systems Hardware-Software Co-Design for Embedded Applications Real-Time Systems and Energy Efficiency Sensor Data Fusion and Autonomous Driving Publications reflect a strong focus on optimizing communication and computation in heterogeneous systems, with recent work emphasizing power savings in multi-core architectures and event-based debugging frameworks. His contributions include frameworks like MPSoCSim for simulating reconfigurable systems, and software-defined FPGA approaches for adaptive computing. He has led research in robotics applications for assisted living environments, combining navigation algorithms with real-time sensor processing. His work also addresses security aspects of FPGA configuration and partial bitstream analysis using machine learning.
Jonas Rabenstein is a Researcher at the Department of Computer Science 4 (Distributed Systems and Operating Systems) within the Technische Fakultät at Friedrich-Alexander-Universität Erlangen-Nürnberg. His work focuses on invasive computing, distributed systems, and system software for many-core architectures. He contributes to the SFB/TRR 89 Invasive Computing project, particularly in developing the Invasive Runtime Support System (iRTSS). His research emphasizes resource arbitration, real-time systems, and embedded architectures. Research Interests: Rabenstein explores challenges in operating systems for heterogeneous hardware, virtual shared memory for MPSoCs, and scalable system software for future many-core processors. His projects address coherence management, task scheduling, and hardware-software co-design to optimize resource utilization. Teaching and Advising: He teaches System Programming courses and has advised multiple theses, including studies on relocating loaders for OctoPOS, system call frameworks, and distributed TCP/IP stacks for manycore systems. His supervision spans Bachelor's and Master's projects, emphasizing practical implementation of distributed and real-time systems. Affiliations: As part of the Distributed Systems and Operating Systems group, he collaborates on projects like OctoPOS and contributes to conferences such as HiPEAC and IPDPSW. His work bridges theoretical system design with practical deployment on emerging architectures.
